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comparison lib/Target/Mips/MipsSEISelLowering.h @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
comparison
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34:e874dbf0ad9d 77:54457678186b
9 // 9 //
10 // Subclass of MipsTargetLowering specialized for mips32/64. 10 // Subclass of MipsTargetLowering specialized for mips32/64.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef MipsSEISELLOWERING_H 14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15 #define MipsSEISELLOWERING_H 15 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
16 16
17 #include "MipsISelLowering.h" 17 #include "MipsISelLowering.h"
18 #include "MipsRegisterInfo.h" 18 #include "MipsRegisterInfo.h"
19 19
20 namespace llvm { 20 namespace llvm {
21 class MipsSETargetLowering : public MipsTargetLowering { 21 class MipsSETargetLowering : public MipsTargetLowering {
22 public: 22 public:
23 explicit MipsSETargetLowering(MipsTargetMachine &TM); 23 explicit MipsSETargetLowering(MipsTargetMachine &TM,
24 const MipsSubtarget &STI);
24 25
25 /// \brief Enable MSA support for the given integer type and Register 26 /// \brief Enable MSA support for the given integer type and Register
26 /// class. 27 /// class.
27 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 28 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
28 /// \brief Enable MSA support for the given floating-point type and 29 /// \brief Enable MSA support for the given floating-point type and
29 /// Register class. 30 /// Register class.
30 void addMSAFloatType(MVT::SimpleValueType Ty, 31 void addMSAFloatType(MVT::SimpleValueType Ty,
31 const TargetRegisterClass *RC); 32 const TargetRegisterClass *RC);
32 33
33 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 34 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
35 unsigned Align = 1,
36 bool *Fast = nullptr) const override;
34 37
35 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36 39
37 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 40 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
38 41
39 virtual MachineBasicBlock * 42 MachineBasicBlock *
40 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 43 EmitInstrWithCustomInserter(MachineInstr *MI,
44 MachineBasicBlock *MBB) const override;
41 45
42 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 46 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
43 EVT VT) const { 47 EVT VT) const override {
44 return false; 48 return false;
45 } 49 }
46 50
47 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 51 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
48 if (VT == MVT::Untyped)
49 return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
50 &Mips::ACC64RegClass;
51
52 return TargetLowering::getRepRegClassFor(VT);
53 }
54 52
55 private: 53 private:
56 virtual bool 54 bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
57 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 55 unsigned NextStackOffset,
58 unsigned NextStackOffset, 56 const MipsFunctionInfo& FI) const override;
59 const MipsFunctionInfo& FI) const;
60 57
61 virtual void 58 void
62 getOpndList(SmallVectorImpl<SDValue> &Ops, 59 getOpndList(SmallVectorImpl<SDValue> &Ops,
63 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 60 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
64 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 61 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
65 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; 62 CallLoweringInfo &CLI, SDValue Callee,
63 SDValue Chain) const override;
66 64
67 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 65 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
68 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 66 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
69 67
70 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 68 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
94 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 92 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
95 MachineBasicBlock *BB) const; 93 MachineBasicBlock *BB) const;
96 /// \brief Emit the INSERT_FD pseudo instruction 94 /// \brief Emit the INSERT_FD pseudo instruction
97 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 95 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
98 MachineBasicBlock *BB) const; 96 MachineBasicBlock *BB) const;
97 /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
98 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
99 MachineBasicBlock *BB,
100 unsigned EltSizeInBytes,
101 bool IsFP) const;
99 /// \brief Emit the FILL_FW pseudo instruction 102 /// \brief Emit the FILL_FW pseudo instruction
100 MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 103 MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
101 MachineBasicBlock *BB) const; 104 MachineBasicBlock *BB) const;
102 /// \brief Emit the FILL_FD pseudo instruction 105 /// \brief Emit the FILL_FD pseudo instruction
103 MachineBasicBlock *emitFILL_FD(MachineInstr *MI, 106 MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
109 MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, 112 MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
110 MachineBasicBlock *BB) const; 113 MachineBasicBlock *BB) const;
111 }; 114 };
112 } 115 }
113 116
114 #endif // MipsSEISELLOWERING_H 117 #endif