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annotate lib/Target/Mips/MipsSEISelLowering.h @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children 60c9769439b8
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1 //===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Subclass of MipsTargetLowering specialized for mips32/64.
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11 //
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12 //===----------------------------------------------------------------------===//
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14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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15 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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16
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17 #include "MipsISelLowering.h"
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18 #include "MipsRegisterInfo.h"
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19
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20 namespace llvm {
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21 class MipsSETargetLowering : public MipsTargetLowering {
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22 public:
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23 explicit MipsSETargetLowering(MipsTargetMachine &TM,
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24 const MipsSubtarget &STI);
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25
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26 /// \brief Enable MSA support for the given integer type and Register
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27 /// class.
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28 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
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29 /// \brief Enable MSA support for the given floating-point type and
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30 /// Register class.
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31 void addMSAFloatType(MVT::SimpleValueType Ty,
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32 const TargetRegisterClass *RC);
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33
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34 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
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35 unsigned Align = 1,
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36 bool *Fast = nullptr) const override;
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37
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38 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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39
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40 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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41
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42 MachineBasicBlock *
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43 EmitInstrWithCustomInserter(MachineInstr *MI,
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44 MachineBasicBlock *MBB) const override;
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45
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46 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
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47 EVT VT) const override {
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48 return false;
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49 }
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50
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51 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
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52
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53 private:
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54 bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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55 unsigned NextStackOffset,
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56 const MipsFunctionInfo& FI) const override;
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57
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58 void
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59 getOpndList(SmallVectorImpl<SDValue> &Ops,
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60 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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61 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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62 CallLoweringInfo &CLI, SDValue Callee,
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63 SDValue Chain) const override;
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64
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65 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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66 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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67
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68 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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69 SelectionDAG &DAG) const;
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70
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71 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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72 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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73 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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74 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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75 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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76 /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
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77 /// depending on the indices in the shuffle.
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78 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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79
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80 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
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81 MachineBasicBlock *BB) const;
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82 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
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83 MachineBasicBlock *BB,
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84 unsigned BranchOp) const;
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85 /// \brief Emit the COPY_FW pseudo instruction
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86 MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
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87 MachineBasicBlock *BB) const;
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88 /// \brief Emit the COPY_FD pseudo instruction
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89 MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
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90 MachineBasicBlock *BB) const;
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91 /// \brief Emit the INSERT_FW pseudo instruction
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92 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
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93 MachineBasicBlock *BB) const;
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94 /// \brief Emit the INSERT_FD pseudo instruction
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95 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
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96 MachineBasicBlock *BB) const;
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97 /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
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98 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
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99 MachineBasicBlock *BB,
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100 unsigned EltSizeInBytes,
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101 bool IsFP) const;
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102 /// \brief Emit the FILL_FW pseudo instruction
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103 MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
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104 MachineBasicBlock *BB) const;
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105 /// \brief Emit the FILL_FD pseudo instruction
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106 MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
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107 MachineBasicBlock *BB) const;
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108 /// \brief Emit the FEXP2_W_1 pseudo instructions.
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109 MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
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110 MachineBasicBlock *BB) const;
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111 /// \brief Emit the FEXP2_D_1 pseudo instructions.
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112 MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
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113 MachineBasicBlock *BB) const;
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114 };
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115 }
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116
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117 #endif