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comparison test/CodeGen/AArch64/tst-br.ll @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children afa8332a0e37
comparison
equal deleted inserted replaced
34:e874dbf0ad9d 77:54457678186b
1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s 1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-atomic-cfg-tidy=0 | FileCheck %s
2 2
3 ; We've got the usual issues with LLVM reordering blocks here. The 3 ; We've got the usual issues with LLVM reordering blocks here. The
4 ; tests are correct for the current order, but who knows when that 4 ; tests are correct for the current order, but who knows when that
5 ; will change. Beware! 5 ; will change. Beware!
6 @var32 = global i32 0 6 @var32 = global i32 0
13 %val64 = load i64* @var64 13 %val64 = load i64* @var64
14 14
15 %tbit0 = and i32 %val, 32768 15 %tbit0 = and i32 %val, 32768
16 %tst0 = icmp ne i32 %tbit0, 0 16 %tst0 = icmp ne i32 %tbit0, 0
17 br i1 %tst0, label %test1, label %end1 17 br i1 %tst0, label %test1, label %end1
18 ; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.LBB0_[0-9]+]] 18 ; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
19 19
20 test1: 20 test1:
21 %tbit1 = and i32 %val, 4096 21 %tbit1 = and i32 %val, 4096
22 %tst1 = icmp ne i32 %tbit1, 0 22 %tst1 = icmp ne i32 %tbit1, 0
23 br i1 %tst1, label %test2, label %end1 23 br i1 %tst1, label %test2, label %end1
25 25
26 test2: 26 test2:
27 %tbit2 = and i64 %val64, 32768 27 %tbit2 = and i64 %val64, 32768
28 %tst2 = icmp ne i64 %tbit2, 0 28 %tst2 = icmp ne i64 %tbit2, 0
29 br i1 %tst2, label %test3, label %end1 29 br i1 %tst2, label %test3, label %end1
30 ; CHECK: tbz {{x[0-9]+}}, #15, [[LBL_end1]] 30 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
31 31
32 test3: 32 test3:
33 %tbit3 = and i64 %val64, 4096 33 %tbit3 = and i64 %val64, 4096
34 %tst3 = icmp ne i64 %tbit3, 0 34 %tst3 = icmp ne i64 %tbit3, 0
35 br i1 %tst3, label %end2, label %end1 35 br i1 %tst3, label %end2, label %end1
36 ; CHECK: tbz {{x[0-9]+}}, #12, [[LBL_end1]] 36 ; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
37 37
38 end2: 38 end2:
39 ; CHECK: movz x0, #1 39 ; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}}
40 ; CHECK-NEXT: ret 40 ; CHECK-NEXT: ret
41 ret i32 1 41 ret i32 1
42 42
43 end1: 43 end1:
44 ; CHECK: [[LBL_end1]]: 44 ; CHECK: [[LBL_end1]]:
45 ; CHECK-NEXT: mov x0, xzr 45 ; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}}
46 ; CHECK-NEXT: ret 46 ; CHECK-NEXT: ret
47 ret i32 0 47 ret i32 0
48 } 48 }