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annotate test/CodeGen/AArch64/tst-br.ll @ 77:54457678186b LLVM3.6

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children afa8332a0e37
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77
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1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-atomic-cfg-tidy=0 | FileCheck %s
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2
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3 ; We've got the usual issues with LLVM reordering blocks here. The
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4 ; tests are correct for the current order, but who knows when that
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5 ; will change. Beware!
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6 @var32 = global i32 0
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7 @var64 = global i64 0
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8
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9 define i32 @test_tbz() {
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10 ; CHECK-LABEL: test_tbz:
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11
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12 %val = load i32* @var32
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13 %val64 = load i64* @var64
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14
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15 %tbit0 = and i32 %val, 32768
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16 %tst0 = icmp ne i32 %tbit0, 0
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17 br i1 %tst0, label %test1, label %end1
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18 ; CHECK: tbz {{w[0-9]+}}, #15, [[LBL_end1:.?LBB0_[0-9]+]]
0
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19
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20 test1:
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21 %tbit1 = and i32 %val, 4096
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22 %tst1 = icmp ne i32 %tbit1, 0
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23 br i1 %tst1, label %test2, label %end1
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24 ; CHECK: tbz {{w[0-9]+}}, #12, [[LBL_end1]]
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25
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26 test2:
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27 %tbit2 = and i64 %val64, 32768
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28 %tst2 = icmp ne i64 %tbit2, 0
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29 br i1 %tst2, label %test3, label %end1
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30 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[LBL_end1]]
0
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31
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32 test3:
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33 %tbit3 = and i64 %val64, 4096
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34 %tst3 = icmp ne i64 %tbit3, 0
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35 br i1 %tst3, label %end2, label %end1
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36 ; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
0
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37
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38 end2:
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39 ; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}}
0
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40 ; CHECK-NEXT: ret
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41 ret i32 1
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42
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43 end1:
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44 ; CHECK: [[LBL_end1]]:
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45 ; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}}
0
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46 ; CHECK-NEXT: ret
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47 ret i32 0
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48 }