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comparison llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll @ 223:5f17cb93ff66 llvm-original

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LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
parents 79ff65ed7e25
children c4bab56944e8
comparison
equal deleted inserted replaced
222:81f6424ef0e3 223:5f17cb93ff66
64 ; CHECK: ; %bb.0: 64 ; CHECK: ; %bb.0:
65 ; CHECK-NEXT: s_mov_b32 s7, s5 65 ; CHECK-NEXT: s_mov_b32 s7, s5
66 ; CHECK-NEXT: s_mov_b32 s6, s4 66 ; CHECK-NEXT: s_mov_b32 s6, s4
67 ; CHECK-NEXT: s_mov_b32 s5, s3 67 ; CHECK-NEXT: s_mov_b32 s5, s3
68 ; CHECK-NEXT: s_mov_b32 s4, s2 68 ; CHECK-NEXT: s_mov_b32 s4, s2
69 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, 16, v1 69 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, 4, v1
70 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, 8, v1
70 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 12, v1 71 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 12, v1
71 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, 8, v1 72 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 16, v1
72 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 4, v1
73 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 20, v1 73 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 20, v1
74 ; CHECK-NEXT: v_mov_b32_e32 v9, s0 74 ; CHECK-NEXT: v_mov_b32_e32 v9, s0
75 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, 16, v2 75 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v2
76 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, 12, v2 76 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, 8, v2
77 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, 8, v2 77 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, 12, v2
78 ; CHECK-NEXT: s_mov_b32 m0, -1 78 ; CHECK-NEXT: s_mov_b32 m0, -1
79 ; CHECK-NEXT: ds_read_b32 v3, v1 79 ; CHECK-NEXT: ds_read_b32 v3, v1
80 ; CHECK-NEXT: ds_read_b32 v5, v4 80 ; CHECK-NEXT: ds_read_b32 v4, v0
81 ; CHECK-NEXT: ds_read_b32 v4, v7 81 ; CHECK-NEXT: ds_read_b32 v5, v5
82 ; CHECK-NEXT: ds_read_b32 v6, v6
83 ; CHECK-NEXT: ds_read_b32 v0, v7
82 ; CHECK-NEXT: ds_read_b32 v1, v8 84 ; CHECK-NEXT: ds_read_b32 v1, v8
83 ; CHECK-NEXT: ds_read_b32 v6, v6 85 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 16, v2
84 ; CHECK-NEXT: ds_read_b32 v0, v0
85 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 4, v2
86 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 20, v2 86 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 20, v2
87 ; CHECK-NEXT: s_waitcnt lgkmcnt(1) 87 ; CHECK-NEXT: s_waitcnt lgkmcnt(2)
88 ; CHECK-NEXT: tbuffer_store_format_xyzw v[3:6], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:264 glc slc 88 ; CHECK-NEXT: tbuffer_store_format_xyzw v[3:6], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:264 glc slc
89 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) 89 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
90 ; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:280 glc slc 90 ; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:280 glc slc
91 ; CHECK-NEXT: s_waitcnt expcnt(0) 91 ; CHECK-NEXT: s_waitcnt expcnt(0)
92 ; CHECK-NEXT: ds_read_b32 v0, v2 92 ; CHECK-NEXT: ds_read_b32 v0, v2
93 ; CHECK-NEXT: ds_read_b32 v2, v12 93 ; CHECK-NEXT: ds_read_b32 v1, v10
94 ; CHECK-NEXT: ds_read_b32 v1, v7 94 ; CHECK-NEXT: ds_read_b32 v2, v11
95 ; CHECK-NEXT: ds_read_b32 v3, v12
96 ; CHECK-NEXT: ds_read_b32 v4, v7
95 ; CHECK-NEXT: ds_read_b32 v5, v8 97 ; CHECK-NEXT: ds_read_b32 v5, v8
96 ; CHECK-NEXT: ds_read_b32 v3, v11
97 ; CHECK-NEXT: ds_read_b32 v4, v10
98 ; CHECK-NEXT: s_waitcnt lgkmcnt(5) 98 ; CHECK-NEXT: s_waitcnt lgkmcnt(5)
99 ; CHECK-NEXT: exp mrt0 off, off, off, off 99 ; CHECK-NEXT: exp mrt0 off, off, off, off
100 ; CHECK-NEXT: s_waitcnt lgkmcnt(1) 100 ; CHECK-NEXT: s_waitcnt lgkmcnt(2)
101 ; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc 101 ; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc
102 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) 102 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
103 ; CHECK-NEXT: tbuffer_store_format_xy v[4:5], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc 103 ; CHECK-NEXT: tbuffer_store_format_xy v[4:5], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc
104 ; CHECK-NEXT: s_endpgm 104 ; CHECK-NEXT: s_endpgm
105 %load1 = load <6 x float>, <6 x float> addrspace(3)* %arg5, align 4 105 %load1 = load <6 x float>, <6 x float> addrspace(3)* %arg5, align 4