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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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3
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4 ; Test that checks for redundant copies to temporary stack slot produced by
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5 ; expandUnalignedLoad.
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6
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7 define amdgpu_vs void @test(<4 x i32> inreg %arg1, <6 x float> addrspace(3)* %arg2) {
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8 ; CHECK-LABEL: test:
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9 ; CHECK: ; %bb.0:
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10 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 12, v0
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11 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, 8, v0
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12 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v0
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13 ; CHECK-NEXT: s_mov_b32 m0, -1
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14 ; CHECK-NEXT: ds_read_b32 v2, v1
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15 ; CHECK-NEXT: ds_read_b32 v1, v4
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16 ; CHECK-NEXT: ds_read_b32 v3, v3
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17 ; CHECK-NEXT: ds_read_b32 v0, v0
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18 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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19 ; CHECK-NEXT: exp mrt0 off, off, off, off
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20 ; CHECK-NEXT: v_mov_b32_e32 v4, 0
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21 ; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
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22 ; CHECK-NEXT: s_endpgm
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23 call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 0, float undef, float undef, float undef, float undef, i1 immarg false, i1 immarg false)
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24 %var1 = load <6 x float>, <6 x float> addrspace(3)* %arg2, align 4
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25 %var2 = shufflevector <6 x float> %var1, <6 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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26 call void @llvm.amdgcn.struct.tbuffer.store.v4f32(<4 x float> %var2, <4 x i32> %arg1, i32 0, i32 0, i32 0, i32 immarg 126, i32 immarg 0)
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27 ret void
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28 }
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29
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30 define amdgpu_vs void @test_2(<4 x i32> inreg %arg1, i32 %arg2, i32 inreg %arg3, <8 x float> addrspace(3)* %arg4) {
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31 ; CHECK-LABEL: test_2:
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32 ; CHECK: ; %bb.0:
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33 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, 28, v1
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34 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, 24, v1
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35 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 20, v1
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36 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 16, v1
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37 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 12, v1
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38 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 8, v1
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39 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v1
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40 ; CHECK-NEXT: s_mov_b32 m0, -1
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41 ; CHECK-NEXT: ds_read_b32 v4, v2
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42 ; CHECK-NEXT: ds_read_b32 v3, v3
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43 ; CHECK-NEXT: ds_read_b32 v2, v6
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44 ; CHECK-NEXT: ds_read_b32 v9, v7
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45 ; CHECK-NEXT: ds_read_b32 v8, v8
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46 ; CHECK-NEXT: ds_read_b32 v7, v10
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47 ; CHECK-NEXT: ds_read_b32 v6, v1
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48 ; CHECK-NEXT: ds_read_b32 v5, v5
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49 ; CHECK-NEXT: s_waitcnt lgkmcnt(1)
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50 ; CHECK-NEXT: tbuffer_store_format_xyzw v[6:9], v0, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc slc
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51 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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52 ; CHECK-NEXT: tbuffer_store_format_xyzw v[2:5], v0, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:16 glc slc
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53 ; CHECK-NEXT: s_endpgm
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54 %load = load <8 x float>, <8 x float> addrspace(3)* %arg4, align 4
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55 %vec1 = shufflevector <8 x float> %load, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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56 call void @llvm.amdgcn.struct.tbuffer.store.v4f32(<4 x float> %vec1, <4 x i32> %arg1, i32 %arg2, i32 0, i32 %arg3, i32 immarg 77, i32 immarg 3)
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57 %vec2 = shufflevector <8 x float> %load, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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58 call void @llvm.amdgcn.struct.tbuffer.store.v4f32(<4 x float> %vec2, <4 x i32> %arg1, i32 %arg2, i32 16, i32 %arg3, i32 immarg 77, i32 immarg 3)
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59 ret void
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60 }
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61
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62 define amdgpu_vs void @test_3(i32 inreg %arg1, i32 inreg %arg2, <4 x i32> inreg %arg3, i32 %arg4, <6 x float> addrspace(3)* %arg5, <6 x float> addrspace(3)* %arg6) {
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63 ; CHECK-LABEL: test_3:
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64 ; CHECK: ; %bb.0:
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65 ; CHECK-NEXT: s_mov_b32 s7, s5
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66 ; CHECK-NEXT: s_mov_b32 s6, s4
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67 ; CHECK-NEXT: s_mov_b32 s5, s3
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68 ; CHECK-NEXT: s_mov_b32 s4, s2
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69 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, 4, v1
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70 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, 8, v1
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71 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 12, v1
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223
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72 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 16, v1
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73 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 20, v1
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74 ; CHECK-NEXT: v_mov_b32_e32 v9, s0
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75 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v2
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76 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, 8, v2
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77 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, 12, v2
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78 ; CHECK-NEXT: s_mov_b32 m0, -1
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79 ; CHECK-NEXT: ds_read_b32 v3, v1
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80 ; CHECK-NEXT: ds_read_b32 v4, v0
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81 ; CHECK-NEXT: ds_read_b32 v5, v5
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82 ; CHECK-NEXT: ds_read_b32 v6, v6
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83 ; CHECK-NEXT: ds_read_b32 v0, v7
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84 ; CHECK-NEXT: ds_read_b32 v1, v8
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85 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, 16, v2
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221
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86 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 20, v2
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223
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87 ; CHECK-NEXT: s_waitcnt lgkmcnt(2)
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88 ; CHECK-NEXT: tbuffer_store_format_xyzw v[3:6], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:264 glc slc
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89 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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90 ; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:280 glc slc
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91 ; CHECK-NEXT: s_waitcnt expcnt(0)
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92 ; CHECK-NEXT: ds_read_b32 v0, v2
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93 ; CHECK-NEXT: ds_read_b32 v1, v10
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94 ; CHECK-NEXT: ds_read_b32 v2, v11
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95 ; CHECK-NEXT: ds_read_b32 v3, v12
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96 ; CHECK-NEXT: ds_read_b32 v4, v7
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97 ; CHECK-NEXT: ds_read_b32 v5, v8
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98 ; CHECK-NEXT: s_waitcnt lgkmcnt(5)
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99 ; CHECK-NEXT: exp mrt0 off, off, off, off
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223
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100 ; CHECK-NEXT: s_waitcnt lgkmcnt(2)
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101 ; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc
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102 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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103 ; CHECK-NEXT: tbuffer_store_format_xy v[4:5], v9, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc
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104 ; CHECK-NEXT: s_endpgm
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105 %load1 = load <6 x float>, <6 x float> addrspace(3)* %arg5, align 4
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106 %vec11 = shufflevector <6 x float> %load1, <6 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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107 call void @llvm.amdgcn.struct.tbuffer.store.v4f32(<4 x float> %vec11, <4 x i32> %arg3, i32 %arg1, i32 264, i32 %arg2, i32 immarg 77, i32 immarg 3)
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108 %vec12 = shufflevector <6 x float> %load1, <6 x float> undef, <2 x i32> <i32 4, i32 5>
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109 call void @llvm.amdgcn.struct.tbuffer.store.v2f32(<2 x float> %vec12, <4 x i32> %arg3, i32 %arg1, i32 280, i32 %arg2, i32 immarg 64, i32 immarg 3)
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110
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111 call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 0, float undef, float undef, float undef, float undef, i1 immarg false, i1 immarg false)
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112
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113 %load2 = load <6 x float>, <6 x float> addrspace(3)* %arg6, align 4
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114 %vec21 = shufflevector <6 x float> %load2, <6 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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115 call void @llvm.amdgcn.struct.tbuffer.store.v4f32(<4 x float> %vec21, <4 x i32> %arg3, i32 %arg1, i32 240, i32 %arg2, i32 immarg 77, i32 immarg 3)
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116 %vec22 = shufflevector <6 x float> %load2, <6 x float> undef, <2 x i32> <i32 4, i32 5>
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117 call void @llvm.amdgcn.struct.tbuffer.store.v2f32(<2 x float> %vec22, <4 x i32> %arg3, i32 %arg1, i32 256, i32 %arg2, i32 immarg 64, i32 immarg 3)
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118
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119 ret void
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120 }
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121
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122 declare void @llvm.amdgcn.struct.tbuffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg, i32 immarg)
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123 declare void @llvm.amdgcn.struct.tbuffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32 immarg, i32 immarg)
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124 declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)
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