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comparison llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll @ 223:5f17cb93ff66 llvm-original

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LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
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children c4bab56944e8
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222:81f6424ef0e3 223:5f17cb93ff66
1 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-opt-vgpr-liverange=true -stop-after=si-opt-vgpr-liverange -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3
4 ; a normal if-else
5 define amdgpu_ps float @else1(i32 %z, float %v) #0 {
6 ; SI-LABEL: name: else1
7 ; SI: bb.0.main_body:
8 ; SI: successors: %bb.3(0x40000000), %bb.1(0x40000000)
9 ; SI: liveins: $vgpr0, $vgpr1
10 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
11 ; SI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
12 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec
13 ; SI: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
14 ; SI: S_BRANCH %bb.3
15 ; SI: bb.1.Flow:
16 ; SI: successors: %bb.2(0x40000000), %bb.4(0x40000000)
17 ; SI: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %13:vgpr_32, %bb.0, %4, %bb.3
18 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, undef %15:vgpr_32, %bb.3
19 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
20 ; SI: S_BRANCH %bb.2
21 ; SI: bb.2.if:
22 ; SI: successors: %bb.4(0x80000000)
23 ; SI: %3:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI1]], [[PHI1]], implicit $mode, implicit $exec
24 ; SI: S_BRANCH %bb.4
25 ; SI: bb.3.else:
26 ; SI: successors: %bb.1(0x80000000)
27 ; SI: %4:vgpr_32 = nofpexcept V_MUL_F32_e32 1077936128, killed [[COPY]], implicit $mode, implicit $exec
28 ; SI: S_BRANCH %bb.1
29 ; SI: bb.4.end:
30 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, %3, %bb.2
31 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
32 ; SI: $vgpr0 = COPY killed [[PHI2]]
33 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0
34 main_body:
35 %cc = icmp sgt i32 %z, 5
36 br i1 %cc, label %if, label %else
37
38 if:
39 %v.if = fmul float %v, 2.0
40 br label %end
41
42 else:
43 %v.else = fmul float %v, 3.0
44 br label %end
45
46 end:
47 %r = phi float [ %v.if, %if ], [ %v.else, %else ]
48 ret float %r
49 }
50
51
52 ; %v was used after if-else
53 define amdgpu_ps float @else2(i32 %z, float %v) #0 {
54 ; SI-LABEL: name: else2
55 ; SI: bb.0.main_body:
56 ; SI: successors: %bb.3(0x40000000), %bb.1(0x40000000)
57 ; SI: liveins: $vgpr0, $vgpr1
58 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
59 ; SI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
60 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec
61 ; SI: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
62 ; SI: S_BRANCH %bb.3
63 ; SI: bb.1.Flow:
64 ; SI: successors: %bb.2(0x40000000), %bb.4(0x40000000)
65 ; SI: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %15:vgpr_32, %bb.0, %4, %bb.3
66 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
67 ; SI: S_BRANCH %bb.2
68 ; SI: bb.2.if:
69 ; SI: successors: %bb.4(0x80000000)
70 ; SI: %3:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[COPY]], [[COPY]], implicit $mode, implicit $exec
71 ; SI: S_BRANCH %bb.4
72 ; SI: bb.3.else:
73 ; SI: successors: %bb.1(0x80000000)
74 ; SI: %4:vgpr_32 = nofpexcept V_MUL_F32_e32 1077936128, [[COPY]], implicit $mode, implicit $exec
75 ; SI: S_BRANCH %bb.1
76 ; SI: bb.4.end:
77 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.1, %3, %bb.2
78 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, %3, %bb.2
79 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
80 ; SI: %14:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI1]], killed [[PHI2]], implicit $mode, implicit $exec
81 ; SI: $vgpr0 = COPY killed %14
82 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0
83 main_body:
84 %cc = icmp sgt i32 %z, 5
85 br i1 %cc, label %if, label %else
86
87 if:
88 %v.if = fmul float %v, 2.0
89 br label %end
90
91 else:
92 %v.else = fmul float %v, 3.0
93 br label %end
94
95 end:
96 %r0 = phi float [ %v.if, %if ], [ %v, %else ]
97 %r1 = phi float [ %v.if, %if ], [ %v.else, %else ]
98 %r2 = fadd float %r0, %r1
99 ret float %r2
100 }
101
102 ; if-else inside loop, %x can be optimized, but %v cannot be.
103 define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 {
104 ; SI-LABEL: name: else3
105 ; SI: bb.0.entry:
106 ; SI: successors: %bb.1(0x80000000)
107 ; SI: liveins: $vgpr0, $vgpr1, $sgpr0, $vgpr2
108 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2
109 ; SI: [[COPY1:%[0-9]+]]:sgpr_32 = COPY killed $sgpr0
110 ; SI: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
111 ; SI: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
112 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 6, killed [[COPY3]], implicit $exec
113 ; SI: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
114 ; SI: bb.1.for.body:
115 ; SI: successors: %bb.4(0x40000000), %bb.2(0x40000000)
116 ; SI: [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %14, %bb.5
117 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %13, %bb.5
118 ; SI: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_GT_I32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
119 ; SI: S_BRANCH %bb.4
120 ; SI: bb.2.Flow:
121 ; SI: successors: %bb.3(0x40000000), %bb.5(0x40000000)
122 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI undef %36:vgpr_32, %bb.1, %10, %bb.4
123 ; SI: [[PHI3:%[0-9]+]]:vgpr_32 = PHI undef %37:vgpr_32, %bb.1, %9, %bb.4
124 ; SI: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, undef %40:vgpr_32, %bb.4
125 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
126 ; SI: S_BRANCH %bb.3
127 ; SI: bb.3.if:
128 ; SI: successors: %bb.5(0x80000000)
129 ; SI: %7:vgpr_32 = nofpexcept V_MUL_F32_e32 [[PHI]], [[COPY2]], implicit $mode, implicit $exec
130 ; SI: %8:vgpr_32, dead %32:sreg_64 = V_ADD_CO_U32_e64 1, killed [[PHI4]], 0, implicit $exec
131 ; SI: S_BRANCH %bb.5
132 ; SI: bb.4.else:
133 ; SI: successors: %bb.2(0x80000000)
134 ; SI: %9:vgpr_32 = nofpexcept V_MUL_F32_e32 [[COPY2]], [[PHI1]], implicit $mode, implicit $exec
135 ; SI: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 killed [[PHI1]], 3, implicit $exec
136 ; SI: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[V_MUL_LO_U32_e64_]]
137 ; SI: S_BRANCH %bb.2
138 ; SI: bb.5.if.end:
139 ; SI: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
140 ; SI: [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI3]], %bb.2, %7, %bb.3
141 ; SI: [[PHI6:%[0-9]+]]:vgpr_32 = PHI [[PHI2]], %bb.2, %8, %bb.3
142 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
143 ; SI: %13:vgpr_32, dead %34:sreg_64 = V_ADD_CO_U32_e64 1, [[PHI6]], 0, implicit $exec
144 ; SI: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 killed [[PHI]], 1, implicit-def dead $scc
145 ; SI: S_CMP_LT_I32 [[S_ADD_I32_]], [[COPY1]], implicit-def $scc
146 ; SI: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
147 ; SI: S_BRANCH %bb.6
148 ; SI: bb.6.for.end:
149 ; SI: %35:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI6]], killed [[PHI5]], implicit $mode, implicit $exec
150 ; SI: $vgpr0 = COPY killed %35
151 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0
152 entry:
153 ; %break = icmp sgt i32 %bound, 0
154 ; br i1 %break, label %for.body, label %for.end
155 br label %for.body
156
157 for.body:
158 %i = phi i32 [ 0, %entry ], [ %inc, %if.end ]
159 %x = phi i32 [ %x0, %entry ], [ %xinc, %if.end ]
160 %cc = icmp sgt i32 %z, 5
161 br i1 %cc, label %if, label %else
162
163 if:
164 %i.tmp = bitcast i32 %i to float
165 %v.if = fmul float %v, %i.tmp
166 %x.if = add i32 %x, 1
167 br label %if.end
168
169 else:
170 %x.tmp = bitcast i32 %x to float
171 %v.else = fmul float %v, %x.tmp
172 %x.else = mul i32 %x, 3
173 br label %if.end
174
175 if.end:
176 %v.endif = phi float [ %v.if, %if ], [ %v.else, %else ]
177 %x.endif = phi i32 [ %x.if, %if ], [ %x.else, %else ]
178
179 %xinc = add i32 %x.endif, 1
180 %inc = add i32 %i, 1
181 %cond = icmp slt i32 %inc, %bound
182 br i1 %cond, label %for.body, label %for.end
183
184 for.end:
185 %x_float = bitcast i32 %x.endif to float
186 %r = fadd float %x_float, %v.endif
187 ret float %r
188 }
189
190 attributes #0 = { nounwind }