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LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
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children c4bab56944e8
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-opt-vgpr-liverange=true -stop-after=si-opt-vgpr-liverange -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; a normal if-else
define amdgpu_ps float @else1(i32 %z, float %v) #0 {
  ; SI-LABEL: name: else1
  ; SI: bb.0.main_body:
  ; SI:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; SI:   liveins: $vgpr0, $vgpr1
  ; SI:   [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
  ; SI:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
  ; SI:   [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec
  ; SI:   [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   S_BRANCH %bb.3
  ; SI: bb.1.Flow:
  ; SI:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
  ; SI:   [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %13:vgpr_32, %bb.0, %4, %bb.3
  ; SI:   [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, undef %15:vgpr_32, %bb.3
  ; SI:   [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   S_BRANCH %bb.2
  ; SI: bb.2.if:
  ; SI:   successors: %bb.4(0x80000000)
  ; SI:   %3:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI1]], [[PHI1]], implicit $mode, implicit $exec
  ; SI:   S_BRANCH %bb.4
  ; SI: bb.3.else:
  ; SI:   successors: %bb.1(0x80000000)
  ; SI:   %4:vgpr_32 = nofpexcept V_MUL_F32_e32 1077936128, killed [[COPY]], implicit $mode, implicit $exec
  ; SI:   S_BRANCH %bb.1
  ; SI: bb.4.end:
  ; SI:   [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, %3, %bb.2
  ; SI:   SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   $vgpr0 = COPY killed [[PHI2]]
  ; SI:   SI_RETURN_TO_EPILOG killed $vgpr0
main_body:
  %cc = icmp sgt i32 %z, 5
  br i1 %cc, label %if, label %else

if:
  %v.if = fmul float %v, 2.0
  br label %end

else:
  %v.else = fmul float %v, 3.0
  br label %end

end:
  %r = phi float [ %v.if, %if ], [ %v.else, %else ]
  ret float %r
}


; %v was used after if-else
define amdgpu_ps float @else2(i32 %z, float %v) #0 {
  ; SI-LABEL: name: else2
  ; SI: bb.0.main_body:
  ; SI:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; SI:   liveins: $vgpr0, $vgpr1
  ; SI:   [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
  ; SI:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
  ; SI:   [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec
  ; SI:   [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   S_BRANCH %bb.3
  ; SI: bb.1.Flow:
  ; SI:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
  ; SI:   [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %15:vgpr_32, %bb.0, %4, %bb.3
  ; SI:   [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   S_BRANCH %bb.2
  ; SI: bb.2.if:
  ; SI:   successors: %bb.4(0x80000000)
  ; SI:   %3:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[COPY]], [[COPY]], implicit $mode, implicit $exec
  ; SI:   S_BRANCH %bb.4
  ; SI: bb.3.else:
  ; SI:   successors: %bb.1(0x80000000)
  ; SI:   %4:vgpr_32 = nofpexcept V_MUL_F32_e32 1077936128, [[COPY]], implicit $mode, implicit $exec
  ; SI:   S_BRANCH %bb.1
  ; SI: bb.4.end:
  ; SI:   [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.1, %3, %bb.2
  ; SI:   [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, %3, %bb.2
  ; SI:   SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   %14:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI1]], killed [[PHI2]], implicit $mode, implicit $exec
  ; SI:   $vgpr0 = COPY killed %14
  ; SI:   SI_RETURN_TO_EPILOG killed $vgpr0
main_body:
  %cc = icmp sgt i32 %z, 5
  br i1 %cc, label %if, label %else

if:
  %v.if = fmul float %v, 2.0
  br label %end

else:
  %v.else = fmul float %v, 3.0
  br label %end

end:
  %r0 = phi float [ %v.if, %if ], [ %v, %else ]
  %r1 = phi float [ %v.if, %if ], [ %v.else, %else ]
  %r2 = fadd float %r0, %r1
  ret float %r2
}

; if-else inside loop, %x can be optimized, but %v cannot be.
define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 {
  ; SI-LABEL: name: else3
  ; SI: bb.0.entry:
  ; SI:   successors: %bb.1(0x80000000)
  ; SI:   liveins: $vgpr0, $vgpr1, $sgpr0, $vgpr2
  ; SI:   [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2
  ; SI:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY killed $sgpr0
  ; SI:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
  ; SI:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
  ; SI:   [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 6, killed [[COPY3]], implicit $exec
  ; SI:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; SI: bb.1.for.body:
  ; SI:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
  ; SI:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %14, %bb.5
  ; SI:   [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %13, %bb.5
  ; SI:   [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_GT_I32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   S_BRANCH %bb.4
  ; SI: bb.2.Flow:
  ; SI:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; SI:   [[PHI2:%[0-9]+]]:vgpr_32 = PHI undef %36:vgpr_32, %bb.1, %10, %bb.4
  ; SI:   [[PHI3:%[0-9]+]]:vgpr_32 = PHI undef %37:vgpr_32, %bb.1, %9, %bb.4
  ; SI:   [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, undef %40:vgpr_32, %bb.4
  ; SI:   [[SI_ELSE:%[0-9]+]]:sreg_64 = SI_ELSE killed [[SI_IF]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   S_BRANCH %bb.3
  ; SI: bb.3.if:
  ; SI:   successors: %bb.5(0x80000000)
  ; SI:   %7:vgpr_32 = nofpexcept V_MUL_F32_e32 [[PHI]], [[COPY2]], implicit $mode, implicit $exec
  ; SI:   %8:vgpr_32, dead %32:sreg_64 = V_ADD_CO_U32_e64 1, killed [[PHI4]], 0, implicit $exec
  ; SI:   S_BRANCH %bb.5
  ; SI: bb.4.else:
  ; SI:   successors: %bb.2(0x80000000)
  ; SI:   %9:vgpr_32 = nofpexcept V_MUL_F32_e32 [[COPY2]], [[PHI1]], implicit $mode, implicit $exec
  ; SI:   [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 killed [[PHI1]], 3, implicit $exec
  ; SI:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[V_MUL_LO_U32_e64_]]
  ; SI:   S_BRANCH %bb.2
  ; SI: bb.5.if.end:
  ; SI:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)
  ; SI:   [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI3]], %bb.2, %7, %bb.3
  ; SI:   [[PHI6:%[0-9]+]]:vgpr_32 = PHI [[PHI2]], %bb.2, %8, %bb.3
  ; SI:   SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; SI:   %13:vgpr_32, dead %34:sreg_64 = V_ADD_CO_U32_e64 1, [[PHI6]], 0, implicit $exec
  ; SI:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 killed [[PHI]], 1, implicit-def dead $scc
  ; SI:   S_CMP_LT_I32 [[S_ADD_I32_]], [[COPY1]], implicit-def $scc
  ; SI:   S_CBRANCH_SCC1 %bb.1, implicit killed $scc
  ; SI:   S_BRANCH %bb.6
  ; SI: bb.6.for.end:
  ; SI:   %35:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI6]], killed [[PHI5]], implicit $mode, implicit $exec
  ; SI:   $vgpr0 = COPY killed %35
  ; SI:   SI_RETURN_TO_EPILOG killed $vgpr0
entry:
;  %break = icmp sgt i32 %bound, 0
;  br i1 %break, label %for.body, label %for.end
  br label %for.body

for.body:
  %i = phi i32 [ 0, %entry ], [ %inc, %if.end ]
  %x = phi i32 [ %x0, %entry ], [ %xinc, %if.end ]
  %cc = icmp sgt i32 %z, 5
  br i1 %cc, label %if, label %else

if:
  %i.tmp = bitcast i32 %i to float
  %v.if = fmul float %v, %i.tmp
  %x.if = add i32 %x, 1
  br label %if.end

else:
  %x.tmp = bitcast i32 %x to float
  %v.else = fmul float %v, %x.tmp
  %x.else = mul i32 %x, 3
  br label %if.end

if.end:
  %v.endif = phi float [ %v.if, %if ], [ %v.else, %else ]
  %x.endif = phi i32 [ %x.if, %if ], [ %x.else, %else ]

  %xinc = add i32 %x.endif, 1
  %inc = add i32 %i, 1
  %cond = icmp slt i32 %inc, %bound
  br i1 %cond, label %for.body, label %for.end

for.end:
  %x_float = bitcast i32 %x.endif to float
  %r = fadd float %x_float, %v.endif
  ret float %r
}

attributes #0 = { nounwind }