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comparison test/CodeGen/X86/extractelement-load.ll @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
comparison
equal deleted inserted replaced
78:af83660cff7b 83:60c9769439b8
1 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s
2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s 2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
3 ; RUN: llc < %s -march=x86-64 -mattr=+avx -mcpu=btver2 | FileCheck %s
3 4
4 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 5 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
5 6
6 define i32 @t(<2 x i64>* %val) nounwind { 7 define i32 @t(<2 x i64>* %val) nounwind {
7 ; CHECK-LABEL: t: 8 ; CHECK-LABEL: t:
27 } 28 }
28 29
29 ; This case could easily end up inf-looping in the DAG combiner due to an 30 ; This case could easily end up inf-looping in the DAG combiner due to an
30 ; low alignment load of the vector which prevents us from reliably forming a 31 ; low alignment load of the vector which prevents us from reliably forming a
31 ; narrow load. 32 ; narrow load.
32 ; FIXME: It would be nice to detect whether the target has fast and legal 33
33 ; unaligned loads and use them here. 34 ; The expected codegen is identical for the AVX case except
35 ; load/store instructions will have a leading 'v', so we don't
36 ; need to special-case the checks.
37
34 define void @t3() { 38 define void @t3() {
35 ; CHECK-LABEL: t3: 39 ; CHECK-LABEL: t3:
36 ; 40 ; CHECK: movupd
37 ; This movs the entire vector, shuffling the high double down. If we fixed the 41 ; CHECK: movhpd
38 ; FIXME above it would just move the high double directly.
39 ; CHECK: movhpd %xmm
40 42
41 bb: 43 bb:
42 %tmp13 = load <2 x double>* undef, align 1 44 %tmp13 = load <2 x double>* undef, align 1
43 %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1 45 %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
44 store double %.sroa.3.24.vec.extract, double* undef, align 8 46 store double %.sroa.3.24.vec.extract, double* undef, align 8
45 unreachable 47 unreachable
46 } 48 }
49
50 ; Case where a load is unary shuffled, then bitcast (to a type with the same
51 ; number of elements) before extractelement.
52 ; This is testing for an assertion - the extraction was assuming that the undef
53 ; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
54 define i64 @t4(<2 x double>* %a) {
55 ; CHECK-LABEL: t4:
56 ; CHECK: mov
57 ; CHECK: ret
58 %b = load <2 x double>* %a, align 16
59 %c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
60 %d = bitcast <2 x double> %c to <2 x i64>
61 %e = extractelement <2 x i64> %d, i32 1
62 ret i64 %e
63 }
64