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annotate test/CodeGen/X86/extractelement-load.ll @ 83:60c9769439b8 LLVM3.7

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
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1 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s
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2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
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3 ; RUN: llc < %s -march=x86-64 -mattr=+avx -mcpu=btver2 | FileCheck %s
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5 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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7 define i32 @t(<2 x i64>* %val) nounwind {
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8 ; CHECK-LABEL: t:
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9 ; CHECK-NOT: movd
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10 ; CHECK: movl 8(
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11 ; CHECK-NEXT: ret
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12 %tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
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13 %tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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14 %tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
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15 ret i32 %tmp4
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16 }
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18 ; Case where extractelement of load ends up as undef.
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19 ; (Making sure this doesn't crash.)
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20 define i32 @t2(<8 x i32>* %xp) {
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21 ; CHECK-LABEL: t2:
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22 ; CHECK: ret
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23 %x = load <8 x i32>* %xp
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24 %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
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25 undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
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26 %y = extractelement <8 x i32> %Shuff68, i32 0
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27 ret i32 %y
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28 }
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30 ; This case could easily end up inf-looping in the DAG combiner due to an
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31 ; low alignment load of the vector which prevents us from reliably forming a
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32 ; narrow load.
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34 ; The expected codegen is identical for the AVX case except
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35 ; load/store instructions will have a leading 'v', so we don't
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36 ; need to special-case the checks.
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37
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38 define void @t3() {
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39 ; CHECK-LABEL: t3:
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40 ; CHECK: movupd
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41 ; CHECK: movhpd
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43 bb:
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44 %tmp13 = load <2 x double>* undef, align 1
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45 %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
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46 store double %.sroa.3.24.vec.extract, double* undef, align 8
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47 unreachable
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48 }
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50 ; Case where a load is unary shuffled, then bitcast (to a type with the same
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51 ; number of elements) before extractelement.
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52 ; This is testing for an assertion - the extraction was assuming that the undef
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53 ; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
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54 define i64 @t4(<2 x double>* %a) {
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55 ; CHECK-LABEL: t4:
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56 ; CHECK: mov
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57 ; CHECK: ret
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58 %b = load <2 x double>* %a, align 16
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59 %c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
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60 %d = bitcast <2 x double> %c to <2 x i64>
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61 %e = extractelement <2 x i64> %d, i32 1
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62 ret i64 %e
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63 }
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