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comparison llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll @ 221:79ff65ed7e25

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LLVM12 Original
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 15 Jun 2021 19:15:29 +0900
parents 1d019706d866
children c4bab56944e8
comparison
equal deleted inserted replaced
220:42394fc6a535 221:79ff65ed7e25
1 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s 1 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
2 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s 2 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
3 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %s 3 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
4 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s 4 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
5 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s 5 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
6 6
7 ; GCN-LABEL: {{^}}gws_sema_v_offset0: 7 ; GCN-LABEL: {{^}}gws_sema_v_offset0:
8 ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} 8 ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
9 ; NOLOOP: ds_gws_sema_v gds{{$}} 9 ; NOLOOP: ds_gws_sema_v gds{{$}}
10 10
11 ; LOOP: s_mov_b32 m0, 0{{$}} 11 ; LOOP: s_mov_b32 m0, 0{{$}}
12 ; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]: 12 ; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]:
13 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 13 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
14 ; GFX8-NEXT: s_nop 0
15 ; LOOP-NEXT: ds_gws_sema_v gds 14 ; LOOP-NEXT: ds_gws_sema_v gds
16 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 15 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) 16 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
18 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 17 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
19 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] 18 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]