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comparison llvm/test/CodeGen/AMDGPU/sdwa-ops.mir @ 221:79ff65ed7e25

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LLVM12 Original
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 15 Jun 2021 19:15:29 +0900
parents 1d019706d866
children 5f17cb93ff66
comparison
equal deleted inserted replaced
220:42394fc6a535 221:79ff65ed7e25
1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s 1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s 2 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s
3 3
4 # test for 3 consecutive _sdwa's 4 # test for 3 consecutive _sdwa's
5 # GFX9-LABEL: name: test1_add_co_sdwa 5 # GFX9-LABEL: name: test1_add_co_sdwa
6 # GFX9: V_ADD_I32_sdwa 6 # GFX9: = nsw V_ADD_CO_U32_sdwa
7 # GFX9-NEXT: = nuw V_ADDC_U32_e32
8 # GFX9: V_ADD_CO_U32_sdwa
7 # GFX9-NEXT: V_ADDC_U32_e32 9 # GFX9-NEXT: V_ADDC_U32_e32
8 # GFX9: V_ADD_I32_sdwa 10 # GFX9: V_ADD_CO_U32_sdwa
9 # GFX9-NEXT: V_ADDC_U32_e32 11 # GFX9-NEXT: V_ADDC_U32_e32
10 # GFX9: V_ADD_I32_sdwa
11 # GFX9-NEXT: V_ADDC_U32_e32
12 --- 12 ---
13 name: test1_add_co_sdwa 13 name: test1_add_co_sdwa
14 tracksRegLiveness: true 14 tracksRegLiveness: true
15 registers: 15 registers:
16 - { id: 0, class: vgpr_32, preferred-register: '' } 16 - { id: 0, class: vgpr_32, preferred-register: '' }
24 %1:sgpr_64 = COPY $sgpr0_sgpr1 24 %1:sgpr_64 = COPY $sgpr0_sgpr1
25 %0:vgpr_32 = COPY $vgpr0 25 %0:vgpr_32 = COPY $vgpr0
26 %22:sreg_32_xm0 = S_MOV_B32 255 26 %22:sreg_32_xm0 = S_MOV_B32 255
27 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 27 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
28 %30:vreg_64 = COPY $sgpr0_sgpr1 28 %30:vreg_64 = COPY $sgpr0_sgpr1
29 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 29 %63:vgpr_32, %65:sreg_64_xexec = nsw V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
30 %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec 30 %64:vgpr_32, dead %66:sreg_64_xexec = nuw V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
31 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 31 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
32 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 32 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
33 33
34 %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 34 %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
35 %163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec 35 %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
36 %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec 36 %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
37 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 37 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
38 GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 38 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
39 39
40 %171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 40 %171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
41 %173:vgpr_32, %175:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %171, 0, implicit $exec 41 %173:vgpr_32, %175:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %171, 0, implicit $exec
42 %174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec 42 %174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec
43 %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1 43 %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1
44 GLOBAL_STORE_DWORDX2_SADDR %30, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 44 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %172, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
45 45
46 ... 46 ...
47 47
48 # test for VCC interference on sdwa, should generate 1 xform only 48 # test for VCC interference on sdwa, should generate 1 xform only
49 # GFX9-LABEL: name: test2_add_co_sdwa 49 # GFX9-LABEL: name: test2_add_co_sdwa
50 # GFX9: V_ADD_I32_sdwa 50 # GFX9: V_ADD_CO_U32_sdwa
51 # GFX9: V_ADDC_U32_e32 51 # GFX9: V_ADDC_U32_e32
52 # GFX9-NOT: V_ADD_I32_sdwa 52 # GFX9-NOT: V_ADD_CO_U32_sdwa
53 # GFX9-NOT: V_ADDC_U32_e32 53 # GFX9-NOT: V_ADDC_U32_e32
54 --- 54 ---
55 name: test2_add_co_sdwa 55 name: test2_add_co_sdwa
56 tracksRegLiveness: true 56 tracksRegLiveness: true
57 registers: 57 registers:
66 %1:sgpr_64 = COPY $sgpr0_sgpr1 66 %1:sgpr_64 = COPY $sgpr0_sgpr1
67 %0:vgpr_32 = COPY $vgpr0 67 %0:vgpr_32 = COPY $vgpr0
68 %22:sreg_32_xm0 = S_MOV_B32 255 68 %22:sreg_32_xm0 = S_MOV_B32 255
69 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 69 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
70 %30:vreg_64 = COPY $sgpr0_sgpr1 70 %30:vreg_64 = COPY $sgpr0_sgpr1
71 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 71 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
72 72
73 %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 73 %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
74 %163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec 74 %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
75 %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec 75 %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
76 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 76 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
77 77
78 %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec 78 %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
79 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 79 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
80 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 80 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
81 81
82 %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 82 %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
83 %163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec 83 %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
84 %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec 84 %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
85 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 85 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
86 GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 86 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
87 87
88 ... 88 ...
89 89
90 # test for CarryOut used, should reject 90 # test for CarryOut used, should reject
91 # GFX9-LABEL: name: test3_add_co_sdwa 91 # GFX9-LABEL: name: test3_add_co_sdwa
92 # GFX9: V_ADD_I32_e64 92 # GFX9: V_ADD_CO_U32_e64
93 # GFX9: V_ADDC_U32_e64 93 # GFX9: V_ADDC_U32_e64
94 # GFX9-NOT: V_ADD_I32_sdwa 94 # GFX9-NOT: V_ADD_CO_U32_sdwa
95 # GFX9-NOT: V_ADDC_U32_e32 95 # GFX9-NOT: V_ADDC_U32_e32
96 --- 96 ---
97 name: test3_add_co_sdwa 97 name: test3_add_co_sdwa
98 tracksRegLiveness: true 98 tracksRegLiveness: true
99 registers: 99 registers:
108 %1:sgpr_64 = COPY $sgpr0_sgpr1 108 %1:sgpr_64 = COPY $sgpr0_sgpr1
109 %0:vgpr_32 = COPY $vgpr0 109 %0:vgpr_32 = COPY $vgpr0
110 %22:sreg_32_xm0 = S_MOV_B32 255 110 %22:sreg_32_xm0 = S_MOV_B32 255
111 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 111 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
112 %30:vreg_64 = COPY $sgpr0_sgpr1 112 %30:vreg_64 = COPY $sgpr0_sgpr1
113 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 113 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
114 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec 114 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
115 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1 115 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1
116 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 116 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
117 117
118 ... 118 ...
119 119
120 # test for CarryIn used more than once, should reject 120 # test for CarryIn used more than once, should reject
121 # GFX9-LABEL: name: test4_add_co_sdwa 121 # GFX9-LABEL: name: test4_add_co_sdwa
122 # GFX9: V_ADD_I32_e64 122 # GFX9: V_ADD_CO_U32_e64
123 # GFX9: V_ADDC_U32_e64 123 # GFX9: V_ADDC_U32_e64
124 # GFX9-NOT: V_ADD_I32_sdwa 124 # GFX9-NOT: V_ADD_CO_U32_sdwa
125 # GFX9-NOT: V_ADDC_U32_e32 125 # GFX9-NOT: V_ADDC_U32_e32
126 --- 126 ---
127 name: test4_add_co_sdwa 127 name: test4_add_co_sdwa
128 tracksRegLiveness: true 128 tracksRegLiveness: true
129 registers: 129 registers:
138 %1:sgpr_64 = COPY $sgpr0_sgpr1 138 %1:sgpr_64 = COPY $sgpr0_sgpr1
139 %0:vgpr_32 = COPY $vgpr0 139 %0:vgpr_32 = COPY $vgpr0
140 %22:sreg_32_xm0 = S_MOV_B32 255 140 %22:sreg_32_xm0 = S_MOV_B32 255
141 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 141 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
142 %30:vreg_64 = COPY $sgpr0_sgpr1 142 %30:vreg_64 = COPY $sgpr0_sgpr1
143 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 143 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
144 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 144 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
145 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1 145 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1
146 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 146 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
147 147
148 148
149 ... 149 ...
150 150
151 # test for simple example, should generate sdwa 151 # test for simple example, should generate sdwa
152 # GFX9-LABEL: name: test5_add_co_sdwa 152 # GFX9-LABEL: name: test5_add_co_sdwa
153 # GFX9: V_ADD_I32_sdwa 153 # GFX9: V_ADD_CO_U32_sdwa
154 # GFX9: V_ADDC_U32_e32 154 # GFX9: V_ADDC_U32_e32
155 --- 155 ---
156 name: test5_add_co_sdwa 156 name: test5_add_co_sdwa
157 tracksRegLiveness: true 157 tracksRegLiveness: true
158 registers: 158 registers:
167 %1:sgpr_64 = COPY $sgpr0_sgpr1 167 %1:sgpr_64 = COPY $sgpr0_sgpr1
168 %0:vgpr_32 = COPY $vgpr0 168 %0:vgpr_32 = COPY $vgpr0
169 %22:sreg_32_xm0 = S_MOV_B32 255 169 %22:sreg_32_xm0 = S_MOV_B32 255
170 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 170 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
171 %30:vreg_64 = COPY $sgpr0_sgpr1 171 %30:vreg_64 = COPY $sgpr0_sgpr1
172 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 172 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
173 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 173 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
174 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 174 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
175 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 175 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
176 176
177 177
178 ... 178 ...
179 179
180 # test for V_ADD_I32_e64 only, should reject 180 # test for V_ADD_CO_U32_e64 only, should reject
181 # GFX9-LABEL: name: test6_add_co_sdwa 181 # GFX9-LABEL: name: test6_add_co_sdwa
182 # GFX9: V_ADD_I32_e64 182 # GFX9: V_ADD_CO_U32_e64
183 # GFX9-NOT: V_ADD_I32_sdwa 183 # GFX9-NOT: V_ADD_CO_U32_sdwa
184 # GFX9-NOT: V_ADDC_U32_e32 184 # GFX9-NOT: V_ADDC_U32_e32
185 --- 185 ---
186 name: test6_add_co_sdwa 186 name: test6_add_co_sdwa
187 tracksRegLiveness: true 187 tracksRegLiveness: true
188 registers: 188 registers:
197 %1:sgpr_64 = COPY $sgpr0_sgpr1 197 %1:sgpr_64 = COPY $sgpr0_sgpr1
198 %0:vgpr_32 = COPY $vgpr0 198 %0:vgpr_32 = COPY $vgpr0
199 %22:sreg_32_xm0 = S_MOV_B32 255 199 %22:sreg_32_xm0 = S_MOV_B32 255
200 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 200 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
201 %30:vreg_64 = COPY $sgpr0_sgpr1 201 %30:vreg_64 = COPY $sgpr0_sgpr1
202 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 202 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
203 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1 203 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1
204 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 204 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
205 205
206 206
207 ... 207 ...
208 208
209 # test for V_ADDC_U32_e64 only, should reject 209 # test for V_ADDC_U32_e64 only, should reject
210 # GFX9-LABEL: name: test7_add_co_sdwa 210 # GFX9-LABEL: name: test7_add_co_sdwa
211 # GFX9: V_ADDC_U32_e64 211 # GFX9: V_ADDC_U32_e64
212 # GFX9-NOT: V_ADD_I32_sdwa 212 # GFX9-NOT: V_ADD_CO_U32_sdwa
213 # GFX9-NOT: V_ADDC_U32_e32 213 # GFX9-NOT: V_ADDC_U32_e32
214 --- 214 ---
215 name: test7_add_co_sdwa 215 name: test7_add_co_sdwa
216 tracksRegLiveness: true 216 tracksRegLiveness: true
217 registers: 217 registers:
230 %24:sreg_64_xexec = COPY $sgpr0_sgpr1 230 %24:sreg_64_xexec = COPY $sgpr0_sgpr1
231 231
232 %30:vreg_64 = COPY $sgpr0_sgpr1 232 %30:vreg_64 = COPY $sgpr0_sgpr1
233 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec 233 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec
234 %62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1 234 %62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1
235 GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 235 GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
236 236
237 237
238 ... 238 ...
239 239
240 # test for $vcc defined between two adds, should not generate 240 # test for $vcc defined between two adds, should not generate
241 # GFX9-LABEL: name: test8_add_co_sdwa 241 # GFX9-LABEL: name: test8_add_co_sdwa
242 # GFX9-NOT: V_ADD_I32_sdwa 242 # GFX9-NOT: V_ADD_CO_U32_sdwa
243 # GFX9: V_ADDC_U32_e64 243 # GFX9: V_ADDC_U32_e64
244 --- 244 ---
245 name: test8_add_co_sdwa 245 name: test8_add_co_sdwa
246 tracksRegLiveness: true 246 tracksRegLiveness: true
247 registers: 247 registers:
256 %1:sgpr_64 = COPY $sgpr0_sgpr1 256 %1:sgpr_64 = COPY $sgpr0_sgpr1
257 %0:vgpr_32 = COPY $vgpr0 257 %0:vgpr_32 = COPY $vgpr0
258 %22:sreg_32_xm0 = S_MOV_B32 255 258 %22:sreg_32_xm0 = S_MOV_B32 255
259 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 259 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
260 %30:vreg_64 = COPY $sgpr0_sgpr1 260 %30:vreg_64 = COPY $sgpr0_sgpr1
261 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 261 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
262 $vcc = COPY %30 262 $vcc = COPY %30
263 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 263 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
264 %31:vreg_64 = COPY $vcc 264 %31:vreg_64 = COPY $vcc
265 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 265 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
266 GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 266 GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
267 267
268 268
269 ... 269 ...
270 270
271 # test for non dead $vcc, should not generate 271 # test for non dead $vcc, should not generate
272 # GFX9-LABEL: name: test9_add_co_sdwa 272 # GFX9-LABEL: name: test9_add_co_sdwa
273 # GFX9-NOT: V_ADD_I32_sdwa 273 # GFX9-NOT: V_ADD_CO_U32_sdwa
274 # GFX9: V_ADDC_U32_e64 274 # GFX9: V_ADDC_U32_e64
275 --- 275 ---
276 name: test9_add_co_sdwa 276 name: test9_add_co_sdwa
277 tracksRegLiveness: true 277 tracksRegLiveness: true
278 registers: 278 registers:
288 %0:vgpr_32 = COPY $vgpr0 288 %0:vgpr_32 = COPY $vgpr0
289 %22:sreg_32_xm0 = S_MOV_B32 255 289 %22:sreg_32_xm0 = S_MOV_B32 255
290 %30:vreg_64 = COPY $sgpr0_sgpr1 290 %30:vreg_64 = COPY $sgpr0_sgpr1
291 $vcc = COPY %30 291 $vcc = COPY %30
292 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 292 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
293 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 293 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
294 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 294 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
295 %31:vreg_64 = COPY $vcc 295 %31:vreg_64 = COPY $vcc
296 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 296 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
297 GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 297 GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
298
298 299
299 ... 300 ...
300 301
301 # test for def $vcc_lo, should not generate 302 # test for def $vcc_lo, should not generate
302 # GFX9-LABEL: name: test10_add_co_sdwa 303 # GFX9-LABEL: name: test10_add_co_sdwa
303 # GFX9-NOT: V_ADD_I32_sdwa 304 # GFX9-NOT: V_ADD_CO_U32_sdwa
304 # GFX9: V_ADDC_U32_e64 305 # GFX9: V_ADDC_U32_e64
305 --- 306 ---
306 name: test10_add_co_sdwa 307 name: test10_add_co_sdwa
307 tracksRegLiveness: true 308 tracksRegLiveness: true
308 registers: 309 registers:
318 %0:vgpr_32 = COPY $vgpr0 319 %0:vgpr_32 = COPY $vgpr0
319 %22:sreg_32_xm0 = S_MOV_B32 255 320 %22:sreg_32_xm0 = S_MOV_B32 255
320 %30:vreg_64 = COPY $sgpr0_sgpr1 321 %30:vreg_64 = COPY $sgpr0_sgpr1
321 $vcc_lo = COPY %30.sub0 322 $vcc_lo = COPY %30.sub0
322 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 323 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
323 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 324 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
324 %31:vgpr_32 = COPY $vcc_lo 325 %31:vgpr_32 = COPY $vcc_lo
325 %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1 326 %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
326 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 327 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
327 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 328 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
328 GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 329 GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
329 330
330 ... 331 ...
331 332
332 # test for read $vcc_hi, should not generate 333 # test for read $vcc_hi, should not generate
333 # GFX9-LABEL: name: test11_add_co_sdwa 334 # GFX9-LABEL: name: test11_add_co_sdwa
334 # GFX9-NOT: V_ADD_I32_sdwa 335 # GFX9-NOT: V_ADD_CO_U32_sdwa
335 # GFX9: V_ADDC_U32_e64 336 # GFX9: V_ADDC_U32_e64
336 --- 337 ---
337 name: test11_add_co_sdwa 338 name: test11_add_co_sdwa
338 tracksRegLiveness: true 339 tracksRegLiveness: true
339 registers: 340 registers:
349 %0:vgpr_32 = COPY $vgpr0 350 %0:vgpr_32 = COPY $vgpr0
350 %22:sreg_32_xm0 = S_MOV_B32 255 351 %22:sreg_32_xm0 = S_MOV_B32 255
351 %30:vreg_64 = COPY $sgpr0_sgpr1 352 %30:vreg_64 = COPY $sgpr0_sgpr1
352 $vcc_hi = COPY %30.sub0 353 $vcc_hi = COPY %30.sub0
353 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 354 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
354 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 355 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
355 %31:vgpr_32 = COPY $vcc_hi 356 %31:vgpr_32 = COPY $vcc_hi
356 %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1 357 %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
357 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 358 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
358 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 359 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
359 GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 360 GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
360 361
361 ... 362 ...
362 363
363 # test for $vcc defined and used between adds, should not generate 364 # test for $vcc defined and used between adds, should not generate
364 # GFX9-LABEL: name: test12_add_co_sdwa 365 # GFX9-LABEL: name: test12_add_co_sdwa
365 # GFX9-NOT: V_ADD_I32_sdwa 366 # GFX9-NOT: V_ADD_CO_U32_sdwa
366 # GFX9: V_ADDC_U32_e64 367 # GFX9: V_ADDC_U32_e64
367 --- 368 ---
368 name: test12_add_co_sdwa 369 name: test12_add_co_sdwa
369 tracksRegLiveness: true 370 tracksRegLiveness: true
370 registers: 371 registers:
379 %1:sgpr_64 = COPY $sgpr0_sgpr1 380 %1:sgpr_64 = COPY $sgpr0_sgpr1
380 %0:vgpr_32 = COPY $vgpr0 381 %0:vgpr_32 = COPY $vgpr0
381 %22:sreg_32_xm0 = S_MOV_B32 255 382 %22:sreg_32_xm0 = S_MOV_B32 255
382 %30:vreg_64 = COPY $sgpr0_sgpr1 383 %30:vreg_64 = COPY $sgpr0_sgpr1
383 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec 384 %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
384 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec 385 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
385 $vcc = COPY %30 386 $vcc = COPY %30
386 %31:vreg_64 = COPY killed $vcc 387 %31:vreg_64 = COPY killed $vcc
387 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec 388 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
388 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 389 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
389 GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) 390 GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, implicit $exec, implicit $exec :: (store 8)
390 391