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comparison lib/Target/Hexagon/HexagonIICScalar.td @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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children c2174574ed3a
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120:1172e4bd9c6f 121:803732b1fca8
1 //===--- HexagonIICScalar.td ----------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 // These itinerary class descriptions are based on the instruction timing
11 // classes as per V62. Curretnly, they are just extracted from
12 // HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
13
14 class PseudoItin {
15 list<InstrItinData> PseudoItin_list = [
16 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 [1, 1, 1]>,
18 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
19 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
20 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
21 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
22 ];
23 }
24
25 class ScalarItin {
26 list<InstrItinData> ScalarItin_list = [
27 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
28 [3, 1], [Hex_FWD, Hex_FWD]>,
29 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
30 [1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
31 ];
32 }