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comparison test/CodeGen/AArch64/tailcall_misched_graph.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc -mcpu=cyclone -debug-only=misched < %s 2>&1 | FileCheck %s 1 ; RUN: llc -mcpu=cyclone -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s
2 2
3 ; REQUIRES: asserts 3 ; REQUIRES: asserts
4 4
5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6 target triple = "arm64-apple-ios7.0.0" 6 target triple = "arm64-apple-ios7.0.0"
35 ; Without this edge the scheduler would be free to move the store accross the load. 35 ; Without this edge the scheduler would be free to move the store accross the load.
36 36
37 ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2> 37 ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
38 ; CHECK-NOT: SU 38 ; CHECK-NOT: SU
39 ; CHECK: Successors: 39 ; CHECK: Successors:
40 ; CHECK: ord SU([[DEPSTOREB:.*]]): Latency=0 40 ; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0
41 ; CHECK: ord SU([[DEPSTOREA:.*]]): Latency=0 41 ; CHECK: SU([[DEPSTOREA:.*]]): Ord Latency=0
42 42
43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4> 43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3> 44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>