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annotate test/CodeGen/AArch64/tailcall_misched_graph.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children 3a76565eade5
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1 ; RUN: llc -mcpu=cyclone -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s
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3 ; REQUIRES: asserts
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5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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6 target triple = "arm64-apple-ios7.0.0"
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8 define void @caller2(i8* %a0, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9) {
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9 entry:
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10 tail call void @callee2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a0)
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11 ret void
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12 }
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14 declare void @callee2(i8*, i8*, i8*, i8*, i8*,
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15 i8*, i8*, i8*, i8*, i8*)
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17 ; Make sure there is a dependence between the load and store to the same stack
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18 ; location during a tail call. Tail calls clobber the incoming argument area and
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19 ; therefore it is not safe to assume argument locations are invariant.
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20 ; PR23459 has a test case that we where miscompiling because of this at the
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21 ; time.
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23 ; CHECK: Frame Objects
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24 ; CHECK: fi#-4: {{.*}} fixed, at location [SP+8]
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25 ; CHECK: fi#-3: {{.*}} fixed, at location [SP]
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26 ; CHECK: fi#-2: {{.*}} fixed, at location [SP+8]
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27 ; CHECK: fi#-1: {{.*}} fixed, at location [SP]
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29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
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30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
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31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4>
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32 ; CHECK: STRXui [[VRB]], <fi#-3>
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33
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34 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
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35 ; Without this edge the scheduler would be free to move the store accross the load.
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37 ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
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38 ; CHECK-NOT: SU
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39 ; CHECK: Successors:
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40 ; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0
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41 ; CHECK: SU([[DEPSTOREA:.*]]): Ord Latency=0
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43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
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44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>