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comparison test/CodeGen/AMDGPU/fptosi.f16.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children
comparison
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120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3 3
4 ; GCN-LABEL: {{^}}fptosi_f16_to_i16 4 ; GCN-LABEL: {{^}}fptosi_f16_to_i16
5 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 5 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
6 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 6 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
7 ; GCN: v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]] 7 ; GCN: v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]
8 ; GCN: buffer_store_short v[[R_I16]] 8 ; GCN: buffer_store_short v[[R_I16]]
9 ; GCN: s_endpgm 9 ; GCN: s_endpgm
10 define void @fptosi_f16_to_i16( 10 define amdgpu_kernel void @fptosi_f16_to_i16(
11 i16 addrspace(1)* %r, 11 i16 addrspace(1)* %r,
12 half addrspace(1)* %a) { 12 half addrspace(1)* %a) {
13 entry: 13 entry:
14 %a.val = load half, half addrspace(1)* %a 14 %a.val = load half, half addrspace(1)* %a
15 %r.val = fptosi half %a.val to i16 15 %r.val = fptosi half %a.val to i16
21 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 21 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
22 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 22 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
23 ; GCN: v_cvt_i32_f32_e32 v[[R_I32:[0-9]+]], v[[A_F32]] 23 ; GCN: v_cvt_i32_f32_e32 v[[R_I32:[0-9]+]], v[[A_F32]]
24 ; GCN: buffer_store_dword v[[R_I32]] 24 ; GCN: buffer_store_dword v[[R_I32]]
25 ; GCN: s_endpgm 25 ; GCN: s_endpgm
26 define void @fptosi_f16_to_i32( 26 define amdgpu_kernel void @fptosi_f16_to_i32(
27 i32 addrspace(1)* %r, 27 i32 addrspace(1)* %r,
28 half addrspace(1)* %a) { 28 half addrspace(1)* %a) {
29 entry: 29 entry:
30 %a.val = load half, half addrspace(1)* %a 30 %a.val = load half, half addrspace(1)* %a
31 %r.val = fptosi half %a.val to i32 31 %r.val = fptosi half %a.val to i32
38 38
39 ; GCN-LABEL: {{^}}fptosi_f16_to_i64 39 ; GCN-LABEL: {{^}}fptosi_f16_to_i64
40 ; GCN: buffer_load_ushort 40 ; GCN: buffer_load_ushort
41 ; GCN: v_cvt_f32_f16_e32 41 ; GCN: v_cvt_f32_f16_e32
42 ; GCN: s_endpgm 42 ; GCN: s_endpgm
43 define void @fptosi_f16_to_i64( 43 define amdgpu_kernel void @fptosi_f16_to_i64(
44 i64 addrspace(1)* %r, 44 i64 addrspace(1)* %r,
45 half addrspace(1)* %a) { 45 half addrspace(1)* %a) {
46 entry: 46 entry:
47 %a.val = load half, half addrspace(1)* %a 47 %a.val = load half, half addrspace(1)* %a
48 %r.val = fptosi half %a.val to i64 48 %r.val = fptosi half %a.val to i64
50 ret void 50 ret void
51 } 51 }
52 52
53 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i16 53 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i16
54 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] 54 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
55 ; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 55
56 ; GCN: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 56 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
57 ; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 57 ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
58 ; GCN: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]] 58 ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
59 ; GCN: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]] 59 ; SI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
60 ; GCN: v_and_b32_e32 v[[R_I16_LO:[0-9]+]], 0xffff, v[[R_I16_0]] 60 ; SI-DAG: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]]
61 ; GCN: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]] 61 ; SI-DAG: v_and_b32_e32 v[[R_I16_LO:[0-9]+]], 0xffff, v[[R_I16_0]]
62 ; GCN: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_HI]], v[[R_I16_LO]] 62 ; SI: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]]
63 ; SI: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_LO]], v[[R_I16_HI]]
64
65 ; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
66 ; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
67 ; VI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
68 ; VI: v_cvt_i32_f32_sdwa v[[R_I16_1:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
69 ; VI: v_or_b32_sdwa v[[R_V2_I16:[0-9]+]], v[[R_I16_0]], v[[R_I16_1]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
70
63 ; GCN: buffer_store_dword v[[R_V2_I16]] 71 ; GCN: buffer_store_dword v[[R_V2_I16]]
64 ; GCN: s_endpgm 72 ; GCN: s_endpgm
65 define void @fptosi_v2f16_to_v2i16( 73
74 define amdgpu_kernel void @fptosi_v2f16_to_v2i16(
66 <2 x i16> addrspace(1)* %r, 75 <2 x i16> addrspace(1)* %r,
67 <2 x half> addrspace(1)* %a) { 76 <2 x half> addrspace(1)* %a) {
68 entry: 77 entry:
69 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 78 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
70 %r.val = fptosi <2 x half> %a.val to <2 x i16> 79 %r.val = fptosi <2 x half> %a.val to <2 x i16>
73 } 82 }
74 83
75 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i32 84 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i32
76 ; GCN: buffer_load_dword 85 ; GCN: buffer_load_dword
77 ; GCN: v_cvt_f32_f16_e32 86 ; GCN: v_cvt_f32_f16_e32
78 ; GCN: v_cvt_f32_f16_e32 87 ; SI: v_cvt_f32_f16_e32
88 ; VI: v_cvt_f32_f16_sdwa
79 ; GCN: v_cvt_i32_f32_e32 89 ; GCN: v_cvt_i32_f32_e32
80 ; GCN: v_cvt_i32_f32_e32 90 ; GCN: v_cvt_i32_f32_e32
81 ; GCN: buffer_store_dwordx2 91 ; GCN: buffer_store_dwordx2
82 ; GCN: s_endpgm 92 ; GCN: s_endpgm
83 define void @fptosi_v2f16_to_v2i32( 93 define amdgpu_kernel void @fptosi_v2f16_to_v2i32(
84 <2 x i32> addrspace(1)* %r, 94 <2 x i32> addrspace(1)* %r,
85 <2 x half> addrspace(1)* %a) { 95 <2 x half> addrspace(1)* %a) {
86 entry: 96 entry:
87 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 97 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
88 %r.val = fptosi <2 x half> %a.val to <2 x i32> 98 %r.val = fptosi <2 x half> %a.val to <2 x i32>
94 ; test checks code generated for 'i64 = fp_to_sint f32'. 104 ; test checks code generated for 'i64 = fp_to_sint f32'.
95 105
96 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i64 106 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i64
97 ; GCN: buffer_load_dword 107 ; GCN: buffer_load_dword
98 ; GCN: v_cvt_f32_f16_e32 108 ; GCN: v_cvt_f32_f16_e32
99 ; GCN: v_cvt_f32_f16_e32 109 ; SI: v_cvt_f32_f16_e32
110 ; VI: v_cvt_f32_f16_sdwa
100 ; GCN: s_endpgm 111 ; GCN: s_endpgm
101 define void @fptosi_v2f16_to_v2i64( 112 define amdgpu_kernel void @fptosi_v2f16_to_v2i64(
102 <2 x i64> addrspace(1)* %r, 113 <2 x i64> addrspace(1)* %r,
103 <2 x half> addrspace(1)* %a) { 114 <2 x half> addrspace(1)* %a) {
104 entry: 115 entry:
105 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 116 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
106 %r.val = fptosi <2 x half> %a.val to <2 x i64> 117 %r.val = fptosi <2 x half> %a.val to <2 x i64>