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121
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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120
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3
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4 ; GCN-LABEL: {{^}}fptosi_f16_to_i16
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5 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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6 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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7 ; GCN: v_cvt_i32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]
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8 ; GCN: buffer_store_short v[[R_I16]]
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9 ; GCN: s_endpgm
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121
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10 define amdgpu_kernel void @fptosi_f16_to_i16(
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120
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11 i16 addrspace(1)* %r,
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12 half addrspace(1)* %a) {
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13 entry:
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14 %a.val = load half, half addrspace(1)* %a
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15 %r.val = fptosi half %a.val to i16
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16 store i16 %r.val, i16 addrspace(1)* %r
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17 ret void
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18 }
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19
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20 ; GCN-LABEL: {{^}}fptosi_f16_to_i32
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21 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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22 ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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23 ; GCN: v_cvt_i32_f32_e32 v[[R_I32:[0-9]+]], v[[A_F32]]
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24 ; GCN: buffer_store_dword v[[R_I32]]
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25 ; GCN: s_endpgm
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121
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26 define amdgpu_kernel void @fptosi_f16_to_i32(
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120
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27 i32 addrspace(1)* %r,
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28 half addrspace(1)* %a) {
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29 entry:
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30 %a.val = load half, half addrspace(1)* %a
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31 %r.val = fptosi half %a.val to i32
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32 store i32 %r.val, i32 addrspace(1)* %r
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33 ret void
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34 }
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35
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36 ; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
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37 ; test checks code generated for 'i64 = fp_to_sint f32'.
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38
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39 ; GCN-LABEL: {{^}}fptosi_f16_to_i64
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40 ; GCN: buffer_load_ushort
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41 ; GCN: v_cvt_f32_f16_e32
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42 ; GCN: s_endpgm
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121
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43 define amdgpu_kernel void @fptosi_f16_to_i64(
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120
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44 i64 addrspace(1)* %r,
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45 half addrspace(1)* %a) {
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46 entry:
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47 %a.val = load half, half addrspace(1)* %a
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48 %r.val = fptosi half %a.val to i64
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49 store i64 %r.val, i64 addrspace(1)* %r
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50 ret void
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51 }
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52
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53 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i16
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54 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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121
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55
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56 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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57 ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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58 ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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59 ; SI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
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60 ; SI-DAG: v_cvt_i32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]]
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61 ; SI-DAG: v_and_b32_e32 v[[R_I16_LO:[0-9]+]], 0xffff, v[[R_I16_0]]
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62 ; SI: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]]
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63 ; SI: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_LO]], v[[R_I16_HI]]
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64
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65 ; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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66 ; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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67 ; VI: v_cvt_i32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
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68 ; VI: v_cvt_i32_f32_sdwa v[[R_I16_1:[0-9]+]], v[[A_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
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69 ; VI: v_or_b32_sdwa v[[R_V2_I16:[0-9]+]], v[[R_I16_0]], v[[R_I16_1]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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70
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120
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71 ; GCN: buffer_store_dword v[[R_V2_I16]]
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72 ; GCN: s_endpgm
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121
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73
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74 define amdgpu_kernel void @fptosi_v2f16_to_v2i16(
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120
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75 <2 x i16> addrspace(1)* %r,
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76 <2 x half> addrspace(1)* %a) {
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77 entry:
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78 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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79 %r.val = fptosi <2 x half> %a.val to <2 x i16>
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80 store <2 x i16> %r.val, <2 x i16> addrspace(1)* %r
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81 ret void
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82 }
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83
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84 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i32
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85 ; GCN: buffer_load_dword
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86 ; GCN: v_cvt_f32_f16_e32
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121
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87 ; SI: v_cvt_f32_f16_e32
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88 ; VI: v_cvt_f32_f16_sdwa
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120
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89 ; GCN: v_cvt_i32_f32_e32
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90 ; GCN: v_cvt_i32_f32_e32
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91 ; GCN: buffer_store_dwordx2
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92 ; GCN: s_endpgm
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121
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93 define amdgpu_kernel void @fptosi_v2f16_to_v2i32(
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120
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94 <2 x i32> addrspace(1)* %r,
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95 <2 x half> addrspace(1)* %a) {
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96 entry:
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97 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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98 %r.val = fptosi <2 x half> %a.val to <2 x i32>
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99 store <2 x i32> %r.val, <2 x i32> addrspace(1)* %r
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100 ret void
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101 }
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102
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103 ; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
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104 ; test checks code generated for 'i64 = fp_to_sint f32'.
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105
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106 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i64
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107 ; GCN: buffer_load_dword
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108 ; GCN: v_cvt_f32_f16_e32
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121
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109 ; SI: v_cvt_f32_f16_e32
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110 ; VI: v_cvt_f32_f16_sdwa
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120
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111 ; GCN: s_endpgm
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121
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112 define amdgpu_kernel void @fptosi_v2f16_to_v2i64(
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120
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113 <2 x i64> addrspace(1)* %r,
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114 <2 x half> addrspace(1)* %a) {
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115 entry:
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116 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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117 %r.val = fptosi <2 x half> %a.val to <2 x i64>
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118 store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
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119 ret void
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120 }
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