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comparison test/CodeGen/AMDGPU/select.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents afa8332a0e37
children
comparison
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120:1172e4bd9c6f 121:803732b1fca8
12 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X 12 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X
13 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY 13 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
14 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY 14 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
15 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW 15 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
16 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW 16 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW
17 define void @select (i32 addrspace(1)* %i32out, float addrspace(1)* %f32out, 17 define amdgpu_kernel void @select (i32 addrspace(1)* %i32out, float addrspace(1)* %f32out,
18 <2 x i32> addrspace(1)* %v2i32out, <2 x float> addrspace(1)* %v2f32out, 18 <2 x i32> addrspace(1)* %v2i32out, <2 x float> addrspace(1)* %v2f32out,
19 <4 x i32> addrspace(1)* %v4i32out, <4 x float> addrspace(1)* %v4f32out, 19 <4 x i32> addrspace(1)* %v4i32out, <4 x float> addrspace(1)* %v4f32out,
20 i32 %cond) { 20 i32 %cond) {
21 entry: 21 entry:
22 br label %for 22 br label %for