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comparison lib/Target/PowerPC/PPCScheduleG4Plus.td @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
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children e4204d083e25
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-1:000000000000 0:95c75e76d11b
1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the itinerary class data for the G4+ (7450) processor.
11 //
12 //===----------------------------------------------------------------------===//
13
14 def IU3 : FuncUnit; // integer unit 3 (7450 simple)
15 def IU4 : FuncUnit; // integer unit 4 (7450 simple)
16
17 def G4PlusItineraries : ProcessorItineraries<
18 [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
19 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
20 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
21 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
22 InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
23 InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
24 InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
25 InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
26 InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
27 InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
28 InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
29 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
30 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
31 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
32 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
33 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
34 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
35 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
36 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
37 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
38 InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
39 InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
40 InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
41 InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
42 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
43 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
44 InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>,
45 InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>,
46 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
47 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
48 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
49 InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>,
50 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
51 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
52 InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
53 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
54 InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
55 InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
56 InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
57 InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
58 InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
59 InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
60 InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
61 InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
62 InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
63 InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
64 InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
65 InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
66 InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
67 InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
68 InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
69 InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
70 InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
71 InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
72 InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
73 InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
74 InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>,
75 InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
76 InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
77 InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
78 InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
79 InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
80 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
81 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
82 InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
83 InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
84 InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
85 InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
86 InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
87 InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
88 ]>;