CbC/CbC_llvm: lib/Target/Mips/MipsInstrInfo.td comparison

comparison lib/Target/Mips/MipsInstrInfo.td @ 95:afa8332a0e37 LLVM3.8

LLVM 3.8

author	Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date	Tue, 13 Oct 2015 17:48:58 +0900
parents	60c9769439b8
children	7d135dc70f03

comparison

equal deleted inserted replaced

-:f3e34b893a5f
+:afa8332a0e37
 def HasMips3     :    Predicate<"Subtarget->hasMips3()">,
 AssemblerPredicate<"FeatureMips3">;
 def HasMips4_32  :    Predicate<"Subtarget->hasMips4_32()">,
 AssemblerPredicate<"FeatureMips4_32">;
 def NotMips4_32  :    Predicate<"!Subtarget->hasMips4_32()">,
-AssemblerPredicate<"FeatureMips4_32">;
+AssemblerPredicate<"!FeatureMips4_32">;
 def HasMips4_32r2 :   Predicate<"Subtarget->hasMips4_32r2()">,
 AssemblerPredicate<"FeatureMips4_32r2">;
 def HasMips5_32r2 :   Predicate<"Subtarget->hasMips5_32r2()">,
 AssemblerPredicate<"FeatureMips5_32r2">;
 def HasMips32    :    Predicate<"Subtarget->hasMips32()">,
 AssemblerPredicate<"FeatureMips32">;
 def HasMips32r2  :    Predicate<"Subtarget->hasMips32r2()">,
 AssemblerPredicate<"FeatureMips32r2">;
+def HasMips32r5  :    Predicate<"Subtarget->hasMips32r5()">,
+AssemblerPredicate<"FeatureMips32r5">;
 def HasMips32r6  :    Predicate<"Subtarget->hasMips32r6()">,
 AssemblerPredicate<"FeatureMips32r6">;
 def NotMips32r6  :    Predicate<"!Subtarget->hasMips32r6()">,
 AssemblerPredicate<"!FeatureMips32r6">;
 def IsGP64bit    :    Predicate<"Subtarget->isGP64bit()">,
 AssemblerPredicate<"FeatureMips64r2">;
 def HasMips64r6  :    Predicate<"Subtarget->hasMips64r6()">,
 AssemblerPredicate<"FeatureMips64r6">;
 def NotMips64r6  :    Predicate<"!Subtarget->hasMips64r6()">,
 AssemblerPredicate<"!FeatureMips64r6">;
+def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
+AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
+def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
+AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
 AssemblerPredicate<"FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
 AssemblerPredicate<"FeatureCnMips">;
-def RelocStatic :     Predicate<"TM.getRelocationModel() == Reloc::Static">,
+def RelocStatic :     Predicate<"TM.getRelocationModel() == Reloc::Static">;
-AssemblerPredicate<"FeatureMips32">;
+def RelocPIC    :     Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
-def RelocPIC    :     Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
-AssemblerPredicate<"FeatureMips32">;
 def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">;
 def HasStdEnc :       Predicate<"Subtarget->hasStandardEncoding()">,
 AssemblerPredicate<"!FeatureMips16">;
 def NotDSP :          Predicate<"!Subtarget->hasDSP()">;
 def InMicroMips    :  Predicate<"Subtarget->inMicroMipsMode()">,
 def NotInMicroMips :  Predicate<"!Subtarget->inMicroMipsMode()">,
 AssemblerPredicate<"!FeatureMicroMips">;
 def IsLE           :  Predicate<"Subtarget->isLittle()">;
 def IsBE           :  Predicate<"!Subtarget->isLittle()">;
 def IsNotNaCl    :    Predicate<"!Subtarget->isTargetNaCl()">;
+def UseTCCInDIV    :  AssemblerPredicate<"FeatureUseTCCInDIV">;
+def HasEVA       :    Predicate<"Subtarget->hasEVA()">,
+AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
+def HasMSA : Predicate<"Subtarget->hasMSA()">,
+AssemblerPredicate<"FeatureMSA">;
 //===----------------------------------------------------------------------===//
 // Mips GPR size adjectives.
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 }
 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
 class ISA_MIPS32R2_NOT_32R6_64R6 {
 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
 }
+class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
 class ISA_MIPS64   { list<Predicate> InsnPredicates = [HasMips64]; }
 class ISA_MIPS64_NOT_64R6 {
 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
 }
 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
+class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
+class ISA_MICROMIPS32R6 {
+list<Predicate> InsnPredicates = [HasMicroMips32r6];
+}
+class ISA_MICROMIPS64R6 {
+list<Predicate> InsnPredicates = [HasMicroMips64r6];
+}
+class ISA_MICROMIPS32_NOT_MIPS32R6 {
+list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
+}
+class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
+class INSN_EVA_NOT_32R6_64R6 {
+list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
+}
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
 // The portions of MIPS-III that were also added to MIPS32 but were removed in
 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
+}
+class ASE_MSA {
+list<Predicate> InsnPredicates = [HasMSA];
+}
+class ASE_MSA64 {
+list<Predicate> InsnPredicates = [HasMSA, HasMips64];
+}
+// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
+// It can be used only on instructions that doesn't inherit PredicateControl.
+class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
+let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
 }
 //===----------------------------------------------------------------------===//
 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
 def calltarget  : Operand<iPTR> {
 let EncoderMethod = "getJumpTargetOpValue";
 let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
+def imm64: Operand<i64>;
 def simm9 : Operand<i32>;
 def simm10 : Operand<i32>;
 def simm11 : Operand<i32>;
 def simm16      : Operand<i32> {
 }
 def uimm20      : Operand<i32> {
 }
+def MipsUImm10AsmOperand : AsmOperandClass {
+let Name = "UImm10";
+let RenderMethod = "addImmOperands";
+let ParserMethod = "parseImm";
+let PredicateMethod = "isUImm<10>";
+}
 def uimm10      : Operand<i32> {
+let ParserMatchClass = MipsUImm10AsmOperand;
 }
 def simm16_64   : Operand<i64> {
 let DecoderMethod = "DecodeSimm16";
 }
 }
 def MipsMemAsmOperand : AsmOperandClass {
 let Name = "Mem";
 let ParserMethod = "parseMemOperand";
+}
+def MipsMemSimm9AsmOperand : AsmOperandClass {
+let Name = "MemOffsetSimm9";
+let SuperClasses = [MipsMemAsmOperand];
+let RenderMethod = "addMemOperands";
+let ParserMethod = "parseMemOperand";
+let PredicateMethod = "isMemWithSimmOffset<9>";
+}
+def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
+let Name = "MemOffsetSimm9GPR";
+let SuperClasses = [MipsMemAsmOperand];
+let RenderMethod = "addMemOperands";
+let ParserMethod = "parseMemOperand";
+let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
 }
 def MipsMemSimm11AsmOperand : AsmOperandClass {
 let Name = "MemOffsetSimm11";
 let SuperClasses = [MipsMemAsmOperand];
 }
 def mem_simm9 : mem_generic {
 let MIOperandInfo = (ops ptr_rc, simm9);
 let EncoderMethod = "getMemEncoding";
+let ParserMatchClass = MipsMemSimm9AsmOperand;
+}
+def mem_simm9gpr : mem_generic {
+let MIOperandInfo = (ops ptr_rc, simm9);
+let EncoderMethod = "getMemEncoding";
+let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
 }
 def mem_simm11 : mem_generic {
 let MIOperandInfo = (ops ptr_rc, simm11);
 let EncoderMethod = "getMemEncoding";
 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
 !strconcat(opstr, "\t$rd, $rt, $rs"),
 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
 opstr>;
-// Load Upper Imediate
+// Load Upper Immediate
 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
 let hasSideEffects = 0;
 let isReMaterializable = 1;
 let DecoderMethod = "DecodeMem";
 let canFoldAsLoad = 1;
 let mayLoad = 1;
 }
-class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
+class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
+SDPatternOperator OpNode = null_frag,
 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
-InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 let DecoderMethod = "DecodeMem";
 let mayStore = 1;
 }
+class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
+InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
+StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
 // Load/Store Left/Right
 let canFoldAsLoad = 1 in
 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
 InstrItinClass Itin> :
 // Conditional Branch
 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
 RegisterOperand RO, bit DelaySlot = 1> :
 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
 !strconcat(opstr, "\t$rs, $rt, $offset"),
-[(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
+[(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
 FrmI, opstr> {
 let isBranch = 1;
 let isTerminator = 1;
 let hasDelaySlot = DelaySlot;
 let Defs = [AT];
 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
 RegisterOperand RO, bit DelaySlot = 1> :
 InstSE<(outs), (ins RO:$rs, opnd:$offset),
 !strconcat(opstr, "\t$rs, $offset"),
-[(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
+[(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
 FrmI, opstr> {
 let isBranch = 1;
 let isTerminator = 1;
 let hasDelaySlot = DelaySlot;
 let Defs = [AT];
 // Jump
 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
 SDPatternOperator targetoperator, string bopstr> :
 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
-[(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
+[(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
 let isTerminator=1;
 let isBarrier=1;
 let hasDelaySlot = 1;
 let DecoderMethod = "DecodeJumpTarget";
 let Defs = [AT];
 }
 // Unconditional branch
 class UncondBranch<Instruction BEQInst> :
-PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
+PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
 let isBranch = 1;
 let isTerminator = 1;
 let isBarrier = 1;
 let hasDelaySlot = 1;
 // Base class for indirect branch and return instruction classes.
 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
 class JumpFR<string opstr, RegisterOperand RO,
 SDPatternOperator operator = null_frag>:
-InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
+InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
 FrmR, opstr>;
 // Indirect branch
 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
 let isBranch = 1;
 // Jump and Link (Call)
 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
 class JumpLink<string opstr, DAGOperand opnd> :
 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
-[(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
+[(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
 let DecoderMethod = "DecodeJumpTarget";
 }
 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
 Register RetReg, RegisterOperand ResRO = RO>:
-PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
+PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
 class JumpLinkReg<string opstr, RegisterOperand RO>:
 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
-[], IIBranch, FrmR>;
+[], II_JALR, FrmR, opstr>;
 class BGEZAL_FT<string opstr, DAGOperand opnd,
 RegisterOperand RO, bit DelaySlot = 1> :
 InstSE<(outs), (ins RO:$rs, opnd:$offset),
-!strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
+!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
 let hasDelaySlot = DelaySlot;
 }
 }
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
 class TailCall<Instruction JumpInst> :
-PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
+PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
 class TailCallReg<RegisterOperand RO, Instruction JRInst,
 RegisterOperand ResRO = RO> :
-PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
+PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
 PseudoInstExpansion<(JRInst ResRO:$rs)>;
 }
 class BAL_BR_Pseudo<Instruction RealInst> :
-PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
+PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
 let isBranch = 1;
 let isTerminator = 1;
 let isBarrier = 1;
 let hasDelaySlot = 1;
 InstrItinClass itin> :
 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
 // Subword Swap
-class SubwordSwap<string opstr, RegisterOperand RO>:
+class SubwordSwap<string opstr, RegisterOperand RO,
-InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
+InstrItinClass itin = NoItinerary>:
-NoItinerary, FrmR, opstr> {
+InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
+FrmR, opstr> {
 let hasSideEffects = 0;
 }
 // Read Hardware
 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
 // Ext and Ins
 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
 SDPatternOperator Op = null_frag>:
 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
 !strconcat(opstr, " $rt, $rs, $pos, $size"),
-[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
+[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
 FrmR, opstr>, ISA_MIPS32R2;
 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
 SDPatternOperator Op = null_frag>:
 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
 !strconcat(opstr, " $rt, $rs, $pos, $size"),
 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
-NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
+II_INS, FrmR, opstr>, ISA_MIPS32R2 {
 let Constraints = "$src = $rt";
 }
 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
 let DecoderMethod = "DecodeMem";
 let mayStore = 1;
 let Constraints = "$rt = $dst";
 }
-class MFC3OP<string asmstr, RegisterOperand RO> :
+class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
-InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
+InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
+!strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
+class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
 class TrapBase<Instruction RealInst>
 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
 PseudoInstExpansion<(RealInst 0, 0)> {
 // MipsI Instructions
 //===----------------------------------------------------------------------===//
 /// Arithmetic Instructions (ALU Immediate)
 let AdditionalPredicates = [NotInMicroMips] in {
-def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
+def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
-add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
+II_ADDIU, immSExt16, add>,
+ADDI_FM<0x9>, IsAsCheapAsAMove;
 }
 def ADDi  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
 ISA_MIPS1_NOT_32R6_64R6;
 def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
 SLTI_FM<0xa>;
 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
 SLTI_FM<0xb>;
 let AdditionalPredicates = [NotInMicroMips] in {
-def ANDi  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
+def ANDi  : MMRel, StdMMR6Rel,
-and>, ADDI_FM<0xc>;
+ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
-}
+ADDI_FM<0xc>;
-def ORi   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
+}
-or>,
+def ORi   : MMRel, StdMMR6Rel,
+ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
 ADDI_FM<0xd>;
-def XORi  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
+def XORi  : MMRel, StdMMR6Rel,
-xor>,
+ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
 ADDI_FM<0xe>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
+let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
-def ADDu  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
+def ADDu  : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
 ADD_FM<0, 0x21>;
 def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
 ADD_FM<0, 0x23>;
+}
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
-def ADD   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
+def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
 def SUB   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
 def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
-def AND   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
+let AdditionalPredicates = [NotInMicroMips] in {
+def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
 ADD_FM<0, 0x24>;
-def OR    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
+def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
 ADD_FM<0, 0x25>;
-def XOR   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
+def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
 ADD_FM<0, 0x26>;
-def NOR   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
+}
+def NOR   : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
 def SLL  : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
 immZExt5>, SRA_FM<0, 0>;
 LW_FM<0x24>;
 def LH  : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
 LW_FM<0x21>;
 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
 let AdditionalPredicates = [NotInMicroMips] in {
-def LW  : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
+def LW  : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
 LW_FM<0x23>;
 }
-def SB  : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
+def SB  : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
+LW_FM<0x28>;
 def SH  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def SW  : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
 }
 }
 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
-def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
+let AdditionalPredicates = [NotInMicroMips] in {
-def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
+def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
-def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
+def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
-def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
+def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
-def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
+def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
-def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
+def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
+def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
+}
 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
 ISA_MIPS2_NOT_32R6_64R6;
 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
 ISA_MIPS2_NOT_32R6_64R6;
 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
 ISA_MIPS2_NOT_32R6_64R6;
 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
 ISA_MIPS2_NOT_32R6_64R6;
-def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
+let AdditionalPredicates = [NotInMicroMips] in {
+def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
+}
 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
 def TRAP : TrapBase<BREAK>;
 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
-def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
+let AdditionalPredicates = [NotInMicroMips] in {
-def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
+def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
+def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
-def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
+}
+def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
+let AdditionalPredicates = [NotInMicroMips] in {
+def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
+}
 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
 AdditionalPredicates = [NotInMicroMips] in {
 def WAIT : WAIT_FT<"wait">, WAIT_FM;
 let AdditionalPredicates = [NotInMicroMips] in {
 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
 }
-// FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
+def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
-def JALX  : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
+ISA_MIPS32_NOT_32R6_64R6;
 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
 ISA_MIPS1_NOT_32R6_64R6;
 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
 class PseudoIndirectBranchBase<RegisterOperand RO> :
-MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
+MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
+II_IndirectBranchPseudo> {
 let isTerminator=1;
 let isBarrier=1;
 let hasDelaySlot = 1;
 let isBranch = 1;
 let isIndirectBranch = 1;
 }
 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
-// Return instructions are matched as a RetRA instruction, then ar expanded
+// Return instructions are matched as a RetRA instruction, then are expanded
 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
 // ISA.
 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
-[], IIBranch> {
+[], II_ReturnPseudo> {
 let isTerminator = 1;
 let isBarrier = 1;
 let hasDelaySlot = 1;
 let isReturn = 1;
 let isCodeGenOnly = 1;
 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
 ISA_MIPS1_NOT_32R6_64R6;
 }
 /// Sign Ext In Register Instructions.
-def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
+def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
-def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
+def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
 /// Count Leading
 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
 ISA_MIPS32_NOT_32R6_64R6;
 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
 ISA_MIPS32_NOT_32R6_64R6;
-/// Word Swap Bytes Within Halfwords
+let AdditionalPredicates = [NotInMicroMips] in {
-def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
+/// Word Swap Bytes Within Halfwords
+def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
+ISA_MIPS32R2;
+}
 /// No operation.
 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
 // FrameIndexes are legalized when they are operands from load/store
 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 /// Move Control Registers From/To CPU Registers
-def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
+def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
-def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
+def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
-def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
+def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
-def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
+def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
 FrmOther, asmstr>;
 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
-(ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
+(OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
+GPR_32 {
+let AdditionalPredicates = [NotInMicroMips];
+}
+def : MipsInstAlias<"move $dst, $src",
+(ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
 GPR_32 {
 let AdditionalPredicates = [NotInMicroMips];
 }
 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
 ISA_MIPS1_NOT_32R6_64R6;
 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
 def : MipsInstAlias<"sltu $rt, $rs, $imm",
 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
 def : MipsInstAlias<"xor $rs, $rt, $imm",
 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
+def : MipsInstAlias<"xor $rs, $imm",
+(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $rt, $imm",
 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $imm",
 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
-def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+}
-def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
-def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
 }
 def : MipsInstAlias<"bnez $rs,$offset",
 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
+def : MipsInstAlias<"bnezl $rs,$offset",
+(BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"beqz $rs,$offset",
 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
+def : MipsInstAlias<"beqzl $rs,$offset",
+(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
+}
 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
+let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"teq $rs, $rt",
 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 def : MipsInstAlias<"tge $rs, $rt",
 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 def : MipsInstAlias<"tgeu $rs, $rt",
 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 def : MipsInstAlias<"tlt $rs, $rt",
 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 def : MipsInstAlias<"tltu $rs, $rt",
 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 def : MipsInstAlias<"tne $rs, $rt",
 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+}
 def  : MipsInstAlias<"sll $rd, $rt, $rs",
 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : MipsInstAlias<"sub, $rd, $rs, $imm",
 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
 (SYNC 0), 1>, ISA_MIPS2;
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
-class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
+class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
 !strconcat(instr_asm, "\t$rt, $imm32")> ;
-def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
+def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
-class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
+class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
+RegisterOperand RO> :
 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
 !strconcat(instr_asm, "\t$rt, $addr")> ;
-def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
+def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
-class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
+class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
 !strconcat(instr_asm, "\t$rt, $imm32")> ;
-def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
+def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
 "jal\t$rd, $rs"> ;
 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
 "jal\t$rs"> ;
+def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+"nor\t$rs, $rt, $imm"> ;
+let hasDelaySlot = 1 in {
+def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
+(ins imm64:$imm64, brtarget:$offset),
+"bne\t$rt, $imm64, $offset">;
+def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
+(ins imm64:$imm64, brtarget:$offset),
+"beq\t$rt, $imm64, $offset">;
+class CondBranchPseudo<string instr_asm> :
+MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
+brtarget:$offset),
+!strconcat(instr_asm, "\t$rs, $rt, $offset")>;
+}
+def BLT : CondBranchPseudo<"blt">;
+def BLE : CondBranchPseudo<"ble">;
+def BGE : CondBranchPseudo<"bge">;
+def BGT : CondBranchPseudo<"bgt">;
+def BLTU : CondBranchPseudo<"bltu">;
+def BLEU : CondBranchPseudo<"bleu">;
+def BGEU : CondBranchPseudo<"bgeu">;
+def BGTU : CondBranchPseudo<"bgtu">;
+def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
+def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
+def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
+def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
+def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
+def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
+def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
+def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
+class CondBranchImmPseudo<string instr_asm> :
+MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
+!strconcat(instr_asm, "\t$rs, $imm, $offset")>;
+def BLTImmMacro  : CondBranchImmPseudo<"blt">;
+def BLEImmMacro  : CondBranchImmPseudo<"ble">;
+def BGEImmMacro  : CondBranchImmPseudo<"bge">;
+def BGTImmMacro  : CondBranchImmPseudo<"bgt">;
+def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
+def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
+def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
+def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;
+def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
+def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
+def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
+def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
+def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
+def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
+def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
+def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
+// FIXME: Predicates are removed because instructions are matched regardless of
+// predicates, because PredicateControl was not in the hierarchy. This was
+// done to emit more precise error message from expansion function.
+// Once the tablegen-erated errors are made better, this needs to be fixed and
+// predicates needs to be restored.
+def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+"div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
+def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+"divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
+def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+"ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
+def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+"ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
+def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+"ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
+def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+"ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 def : WrapperPat<texternalsym, ADDiu, GPR32>;
 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
 def : WrapperPat<tjumptable, ADDiu, GPR32>;
 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
+let AdditionalPredicates = [NotInMicroMips] in {
 // Mips does not have "not", so we expand our way
 def : MipsPat<(not GPR32:$in),
 (NOR GPR32Opnd:$in, ZERO)>;
+}
 // extended loads
 def : MipsPat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
 def : MipsPat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
 // MSA
 include "MipsMSAInstrFormats.td"
 include "MipsMSAInstrInfo.td"
+// EVA
+include "MipsEVAInstrFormats.td"
+include "MipsEVAInstrInfo.td"
 // Micromips
 include "MicroMipsInstrFormats.td"
 include "MicroMipsInstrInfo.td"
 include "MicroMipsInstrFPU.td"
+// Micromips r6
+include "MicroMips32r6InstrFormats.td"
+include "MicroMips32r6InstrInfo.td"
+// Micromips64 r6
+include "MicroMips64r6InstrFormats.td"
+include "MicroMips64r6InstrInfo.td"
+// Micromips DSP
+include "MicroMipsDSPInstrFormats.td"
+include "MicroMipsDSPInstrInfo.td"

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MipsInstrInfo.td @ 95:afa8332a0e37 LLVM3.8