0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
4 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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5 // This file is distributed under the University of Illinois Open Source
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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6 // License. See LICENSE.TXT for details.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
7 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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10 // This file contains the Mips implementation of the TargetInstrInfo class.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
11 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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12 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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15 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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16 // Mips profiles and nodes
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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17 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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18
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21 SDTCisSameAs<1, 2>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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22 SDTCisSameAs<3, 4>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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23 SDTCisInt<4>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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30 SDTCisSameAs<1, 2>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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35
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 SDTCisSameAs<0, 4>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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48 SDTCisSameAs<0, 2>]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 // Call
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53 SDNPVariadic]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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54
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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55 // Tail call
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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58
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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59 // Hi and Lo nodes are used to handle global addresses. Used on
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
61 // static model. (nothing to do with Mips Registers Hi and Lo)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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66 // TlsGd node is used to handle General Dynamic TLS
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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68
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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72
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
73 // Thread pointer
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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75
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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76 // Return
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
79
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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80 // These are target-independent nodes, but have target-specific formats.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
84 [SDNPHasChain, SDNPSideEffect,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
85 SDNPOptInGlue, SDNPOutGlue]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
86
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 // Nodes used to extract LO/HI registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
90
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
91 // Node used to insert 32-bit integers to LOHI register pair.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
93
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
94 // Mult nodes.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
97
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
98 // MAdd*/MSub* nodes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
103
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
104 // DivRem(u) nodes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
108 [SDNPOutGlue]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
110 [SDNPOutGlue]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
111
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
112 // Target constant nodes that are not part of any isel patterns and remain
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
113 // unchanged can cause instructions with illegal operands to be emitted.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
114 // Wrapper node patterns give the instruction selector a chance to replace
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
115 // target constant nodes that would otherwise remain unchanged with ADDiu
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
116 // nodes. Without these wrapper node patterns, the following conditional move
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
118 // compiled:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
119 // movn %got(d)($gp), %got(c)($gp), $4
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
120 // This instruction is illegal since movn can take only register operands.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
121
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
123
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
125
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
128
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
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135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
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137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
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142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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145
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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146 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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147 // Mips Instruction Predicate Definitions.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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148 //===----------------------------------------------------------------------===//
|
|
77
|
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
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150 AssemblerPredicate<"FeatureMips2">;
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151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
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152 AssemblerPredicate<"FeatureMips3_32">;
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153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
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154 AssemblerPredicate<"FeatureMips3_32r2">;
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155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
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156 AssemblerPredicate<"FeatureMips3">;
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157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
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158 AssemblerPredicate<"FeatureMips4_32">;
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83
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159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
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95
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160 AssemblerPredicate<"!FeatureMips4_32">;
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77
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161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
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162 AssemblerPredicate<"FeatureMips4_32r2">;
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163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
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164 AssemblerPredicate<"FeatureMips5_32r2">;
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165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
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166 AssemblerPredicate<"FeatureMips32">;
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77
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167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
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168 AssemblerPredicate<"FeatureMips32r2">;
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95
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169 def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
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170 AssemblerPredicate<"FeatureMips32r5">;
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77
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171 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
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172 AssemblerPredicate<"FeatureMips32r6">;
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173 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
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174 AssemblerPredicate<"!FeatureMips32r6">;
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175 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
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176 AssemblerPredicate<"FeatureGP64Bit">;
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177 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
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178 AssemblerPredicate<"!FeatureGP64Bit">;
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179 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
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180 AssemblerPredicate<"FeatureMips64">;
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77
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181 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
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182 AssemblerPredicate<"FeatureMips64r2">;
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77
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183 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
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184 AssemblerPredicate<"FeatureMips64r6">;
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185 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
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186 AssemblerPredicate<"!FeatureMips64r6">;
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95
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187 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
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188 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
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189 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
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190 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
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77
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191 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
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192 AssemblerPredicate<"FeatureMips16">;
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77
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193 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
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194 AssemblerPredicate<"FeatureCnMips">;
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95
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195 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
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196 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
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77
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197 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
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198 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
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199 AssemblerPredicate<"!FeatureMips16">;
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77
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200 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
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201 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
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202 AssemblerPredicate<"FeatureMicroMips">;
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77
|
203 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
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204 AssemblerPredicate<"!FeatureMicroMips">;
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77
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205 def IsLE : Predicate<"Subtarget->isLittle()">;
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206 def IsBE : Predicate<"!Subtarget->isLittle()">;
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207 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
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95
|
208 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
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209 def HasEVA : Predicate<"Subtarget->hasEVA()">,
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210 AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
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211 def HasMSA : Predicate<"Subtarget->hasMSA()">,
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212 AssemblerPredicate<"FeatureMSA">;
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213
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77
|
214
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|
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215 //===----------------------------------------------------------------------===//
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|
216 // Mips GPR size adjectives.
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217 // They are mutually exclusive.
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218 //===----------------------------------------------------------------------===//
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219
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220 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
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221 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
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222
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|
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223 //===----------------------------------------------------------------------===//
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224 // Mips ISA/ASE membership and instruction group membership adjectives.
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225 // They are mutually exclusive.
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226 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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227
|
|
77
|
228 // FIXME: I'd prefer to use additive predicates to build the instruction sets
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229 // but we are short on assembler feature bits at the moment. Using a
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|
230 // subtractive predicate will hopefully keep us under the 32 predicate
|
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231 // limit long enough to develop an alternative way to handle P1||P2
|
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|
232 // predicates.
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83
|
233 class ISA_MIPS1_NOT_4_32 {
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234 list<Predicate> InsnPredicates = [NotMips4_32];
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|
235 }
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77
|
236 class ISA_MIPS1_NOT_32R6_64R6 {
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237 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
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238 }
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239 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
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240 class ISA_MIPS2_NOT_32R6_64R6 {
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241 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
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242 }
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243 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
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244 class ISA_MIPS3_NOT_32R6_64R6 {
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245 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
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246 }
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247 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
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248 class ISA_MIPS32_NOT_32R6_64R6 {
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249 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
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|
250 }
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|
251 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
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252 class ISA_MIPS32R2_NOT_32R6_64R6 {
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253 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
|
|
|
254 }
|
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95
|
255 class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
|
|
77
|
256 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
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257 class ISA_MIPS64_NOT_64R6 {
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258 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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259 }
|
|
77
|
260 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
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|
|
261 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
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|
|
262 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
|
|
95
|
263 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
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|
|
264 class ISA_MICROMIPS32R6 {
|
|
|
265 list<Predicate> InsnPredicates = [HasMicroMips32r6];
|
|
|
266 }
|
|
|
267 class ISA_MICROMIPS64R6 {
|
|
|
268 list<Predicate> InsnPredicates = [HasMicroMips64r6];
|
|
|
269 }
|
|
|
270 class ISA_MICROMIPS32_NOT_MIPS32R6 {
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|
271 list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
|
|
|
272 }
|
|
|
273
|
|
|
274 class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
|
|
|
275 class INSN_EVA_NOT_32R6_64R6 {
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|
|
276 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
|
|
|
277 }
|
|
77
|
278
|
|
|
279 // The portions of MIPS-III that were also added to MIPS32
|
|
|
280 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
|
|
|
281
|
|
|
282 // The portions of MIPS-III that were also added to MIPS32 but were removed in
|
|
|
283 // MIPS32r6 and MIPS64r6.
|
|
|
284 class INSN_MIPS3_32_NOT_32R6_64R6 {
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|
|
285 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
|
|
|
286 }
|
|
|
287
|
|
|
288 // The portions of MIPS-III that were also added to MIPS32
|
|
|
289 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
|
|
|
290
|
|
|
291 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
|
|
|
292 // MIPS32r6 and MIPS64r6.
|
|
|
293 class INSN_MIPS4_32_NOT_32R6_64R6 {
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|
|
294 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
|
|
|
295 }
|
|
|
296
|
|
|
297 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
|
|
|
298 // MIPS32r6 and MIPS64r6.
|
|
|
299 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
|
|
|
300 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
|
|
|
301 }
|
|
|
302
|
|
|
303 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
|
|
|
304 // MIPS32r6 and MIPS64r6.
|
|
|
305 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
|
|
|
306 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
|
|
|
307 }
|
|
|
308
|
|
95
|
309 class ASE_MSA {
|
|
|
310 list<Predicate> InsnPredicates = [HasMSA];
|
|
|
311 }
|
|
|
312
|
|
|
313 class ASE_MSA64 {
|
|
|
314 list<Predicate> InsnPredicates = [HasMSA, HasMips64];
|
|
|
315 }
|
|
|
316
|
|
|
317 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
|
|
|
318 // It can be used only on instructions that doesn't inherit PredicateControl.
|
|
|
319 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
|
|
|
320 let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
|
|
|
321 }
|
|
|
322
|
|
77
|
323 //===----------------------------------------------------------------------===//
|
|
|
324
|
|
|
325 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
|
|
|
326 let EncodingPredicates = [HasStdEnc];
|
|
|
327 }
|
|
|
328
|
|
|
329 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
|
|
|
330 InstAlias<Asm, Result, Emit>, PredicateControl;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
changeset
|
331
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
332 class IsCommutable {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
333 bit isCommutable = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
334 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
335
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
336 class IsBranch {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
337 bit isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
338 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
339
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
340 class IsReturn {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
341 bit isReturn = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
342 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
343
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
344 class IsCall {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
345 bit isCall = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
346 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
347
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
348 class IsTailCall {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
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|
349 bit isCall = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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changeset
|
350 bit isTerminator = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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changeset
|
351 bit isReturn = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
changeset
|
352 bit isBarrier = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
changeset
|
353 bit hasExtraSrcRegAllocReq = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
changeset
|
354 bit isCodeGenOnly = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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changeset
|
355 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
356
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
357 class IsAsCheapAsAMove {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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changeset
|
358 bit isAsCheapAsAMove = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
359 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
360
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
361 class NeverHasSideEffects {
|
|
83
|
362 bit hasSideEffects = 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
363 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
364
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
365 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
366 // Instruction format superclass
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
367 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
368
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
369 include "MipsInstrFormats.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
370
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
371 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
372 // Mips Operand, Complex Patterns and Transformations Definitions.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
373 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
374
|
|
77
|
375 def MipsJumpTargetAsmOperand : AsmOperandClass {
|
|
|
376 let Name = "JumpTarget";
|
|
|
377 let ParserMethod = "parseJumpTarget";
|
|
|
378 let PredicateMethod = "isImm";
|
|
|
379 let RenderMethod = "addImmOperands";
|
|
|
380 }
|
|
|
381
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
382 // Instruction operand types
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
383 def jmptarget : Operand<OtherVT> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
384 let EncoderMethod = "getJumpTargetOpValue";
|
|
77
|
385 let ParserMatchClass = MipsJumpTargetAsmOperand;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
386 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
387 def brtarget : Operand<OtherVT> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
388 let EncoderMethod = "getBranchTargetOpValue";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
389 let OperandType = "OPERAND_PCREL";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
390 let DecoderMethod = "DecodeBranchTarget";
|
|
77
|
391 let ParserMatchClass = MipsJumpTargetAsmOperand;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
392 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
393 def calltarget : Operand<iPTR> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
394 let EncoderMethod = "getJumpTargetOpValue";
|
|
77
|
395 let ParserMatchClass = MipsJumpTargetAsmOperand;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
397
|
|
95
|
398 def imm64: Operand<i64>;
|
|
|
399
|
|
77
|
400 def simm9 : Operand<i32>;
|
|
|
401 def simm10 : Operand<i32>;
|
|
|
402 def simm11 : Operand<i32>;
|
|
|
403
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
404 def simm16 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 let DecoderMethod= "DecodeSimm16";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
407
|
|
77
|
408 def simm19_lsl2 : Operand<i32> {
|
|
|
409 let EncoderMethod = "getSimm19Lsl2Encoding";
|
|
|
410 let DecoderMethod = "DecodeSimm19Lsl2";
|
|
|
411 let ParserMatchClass = MipsJumpTargetAsmOperand;
|
|
|
412 }
|
|
|
413
|
|
|
414 def simm18_lsl3 : Operand<i32> {
|
|
|
415 let EncoderMethod = "getSimm18Lsl3Encoding";
|
|
|
416 let DecoderMethod = "DecodeSimm18Lsl3";
|
|
|
417 let ParserMatchClass = MipsJumpTargetAsmOperand;
|
|
|
418 }
|
|
|
419
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
420 def simm20 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
421 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
422
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
423 def uimm20 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
424 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
425
|
|
95
|
426 def MipsUImm10AsmOperand : AsmOperandClass {
|
|
|
427 let Name = "UImm10";
|
|
|
428 let RenderMethod = "addImmOperands";
|
|
|
429 let ParserMethod = "parseImm";
|
|
|
430 let PredicateMethod = "isUImm<10>";
|
|
|
431 }
|
|
|
432
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
433 def uimm10 : Operand<i32> {
|
|
95
|
434 let ParserMatchClass = MipsUImm10AsmOperand;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 def simm16_64 : Operand<i64> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438 let DecoderMethod = "DecodeSimm16";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
439 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
440
|
|
77
|
441 // Zero
|
|
|
442 def uimmz : Operand<i32> {
|
|
|
443 let PrintMethod = "printUnsignedImm";
|
|
|
444 }
|
|
|
445
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
446 // Unsigned Operand
|
|
77
|
447 def uimm2 : Operand<i32> {
|
|
|
448 let PrintMethod = "printUnsignedImm";
|
|
|
449 }
|
|
|
450
|
|
|
451 def uimm3 : Operand<i32> {
|
|
|
452 let PrintMethod = "printUnsignedImm";
|
|
|
453 }
|
|
|
454
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
455 def uimm5 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
456 let PrintMethod = "printUnsignedImm";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
457 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
458
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
459 def uimm6 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
460 let PrintMethod = "printUnsignedImm";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
461 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
462
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
463 def uimm16 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
464 let PrintMethod = "printUnsignedImm";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
466
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
467 def pcrel16 : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
468 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470 def MipsMemAsmOperand : AsmOperandClass {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
471 let Name = "Mem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
472 let ParserMethod = "parseMemOperand";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
473 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
474
|
|
95
|
475 def MipsMemSimm9AsmOperand : AsmOperandClass {
|
|
|
476 let Name = "MemOffsetSimm9";
|
|
|
477 let SuperClasses = [MipsMemAsmOperand];
|
|
|
478 let RenderMethod = "addMemOperands";
|
|
|
479 let ParserMethod = "parseMemOperand";
|
|
|
480 let PredicateMethod = "isMemWithSimmOffset<9>";
|
|
|
481 }
|
|
|
482
|
|
|
483 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
|
|
|
484 let Name = "MemOffsetSimm9GPR";
|
|
|
485 let SuperClasses = [MipsMemAsmOperand];
|
|
|
486 let RenderMethod = "addMemOperands";
|
|
|
487 let ParserMethod = "parseMemOperand";
|
|
|
488 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
|
|
|
489 }
|
|
|
490
|
|
77
|
491 def MipsMemSimm11AsmOperand : AsmOperandClass {
|
|
|
492 let Name = "MemOffsetSimm11";
|
|
|
493 let SuperClasses = [MipsMemAsmOperand];
|
|
|
494 let RenderMethod = "addMemOperands";
|
|
|
495 let ParserMethod = "parseMemOperand";
|
|
|
496 let PredicateMethod = "isMemWithSimmOffset<11>";
|
|
83
|
497 }
|
|
|
498
|
|
|
499 def MipsMemSimm16AsmOperand : AsmOperandClass {
|
|
|
500 let Name = "MemOffsetSimm16";
|
|
|
501 let SuperClasses = [MipsMemAsmOperand];
|
|
|
502 let RenderMethod = "addMemOperands";
|
|
|
503 let ParserMethod = "parseMemOperand";
|
|
|
504 let PredicateMethod = "isMemWithSimmOffset<16>";
|
|
77
|
505 }
|
|
|
506
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507 def MipsInvertedImmoperand : AsmOperandClass {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
508 let Name = "InvNum";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509 let RenderMethod = "addImmOperands";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510 let ParserMethod = "parseInvNum";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
511 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
512
|
|
77
|
513 def InvertedImOperand : Operand<i32> {
|
|
|
514 let ParserMatchClass = MipsInvertedImmoperand;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
516
|
|
77
|
517 def InvertedImOperand64 : Operand<i64> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
518 let ParserMatchClass = MipsInvertedImmoperand;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
519 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520
|
|
33
|
521 class mem_generic : Operand<iPTR> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
522 let PrintMethod = "printMemOperand";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
523 let MIOperandInfo = (ops ptr_rc, simm16);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
524 let EncoderMethod = "getMemEncoding";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
525 let ParserMatchClass = MipsMemAsmOperand;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526 let OperandType = "OPERAND_MEMORY";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
527 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
528
|
|
33
|
529 // Address operand
|
|
|
530 def mem : mem_generic;
|
|
|
531
|
|
|
532 // MSA specific address operand
|
|
|
533 def mem_msa : mem_generic {
|
|
77
|
534 let MIOperandInfo = (ops ptr_rc, simm10);
|
|
33
|
535 let EncoderMethod = "getMSAMemEncoding";
|
|
|
536 }
|
|
|
537
|
|
77
|
538 def mem_simm9 : mem_generic {
|
|
|
539 let MIOperandInfo = (ops ptr_rc, simm9);
|
|
|
540 let EncoderMethod = "getMemEncoding";
|
|
95
|
541 let ParserMatchClass = MipsMemSimm9AsmOperand;
|
|
|
542 }
|
|
|
543
|
|
|
544 def mem_simm9gpr : mem_generic {
|
|
|
545 let MIOperandInfo = (ops ptr_rc, simm9);
|
|
|
546 let EncoderMethod = "getMemEncoding";
|
|
|
547 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
|
|
77
|
548 }
|
|
|
549
|
|
|
550 def mem_simm11 : mem_generic {
|
|
|
551 let MIOperandInfo = (ops ptr_rc, simm11);
|
|
|
552 let EncoderMethod = "getMemEncoding";
|
|
|
553 let ParserMatchClass = MipsMemSimm11AsmOperand;
|
|
|
554 }
|
|
|
555
|
|
83
|
556 def mem_simm16 : mem_generic {
|
|
|
557 let MIOperandInfo = (ops ptr_rc, simm16);
|
|
|
558 let EncoderMethod = "getMemEncoding";
|
|
|
559 let ParserMatchClass = MipsMemSimm16AsmOperand;
|
|
|
560 }
|
|
|
561
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
562 def mem_ea : Operand<iPTR> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
563 let PrintMethod = "printMemOperandEA";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
564 let MIOperandInfo = (ops ptr_rc, simm16);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
565 let EncoderMethod = "getMemEncoding";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
566 let OperandType = "OPERAND_MEMORY";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
567 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
568
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
569 def PtrRC : Operand<iPTR> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
570 let MIOperandInfo = (ops ptr_rc);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
571 let DecoderMethod = "DecodePtrRegisterClass";
|
|
77
|
572 let ParserMatchClass = GPR32AsmOperand;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
573 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
574
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
575 // size operand of ext instruction
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
576 def size_ext : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
577 let EncoderMethod = "getSizeExtEncoding";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
578 let DecoderMethod = "DecodeExtSize";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
579 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
580
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
581 // size operand of ins instruction
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
582 def size_ins : Operand<i32> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
583 let EncoderMethod = "getSizeInsEncoding";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
584 let DecoderMethod = "DecodeInsSize";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
585 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
586
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
587 // Transformation Function - get the lower 16 bits.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
588 def LO16 : SDNodeXForm<imm, [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
589 return getImm(N, N->getZExtValue() & 0xFFFF);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
590 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
591
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
592 // Transformation Function - get the higher 16 bits.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
593 def HI16 : SDNodeXForm<imm, [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
594 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
595 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
596
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
597 // Plus 1.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
598 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
599
|
|
77
|
600 // Node immediate is zero (e.g. insve.d)
|
|
|
601 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
|
|
|
602
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
603 // Node immediate fits as 16-bit sign extended on target immediate.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
604 // e.g. addi, andi
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
605 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
606
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
607 // Node immediate fits as 16-bit sign extended on target immediate.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
608 // e.g. addi, andi
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
609 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
610
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
611 // Node immediate fits as 15-bit sign extended on target immediate.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
612 // e.g. addi, andi
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
613 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
614
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
615 // Node immediate fits as 16-bit zero extended on target immediate.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
616 // The LO16 param means that only the lower 16 bits of the node
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
617 // immediate are caught.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
618 // e.g. addiu, sltiu
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
619 def immZExt16 : PatLeaf<(imm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
620 if (N->getValueType(0) == MVT::i32)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
621 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
622 else
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
623 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
624 }], LO16>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
625
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
626 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
627 def immLow16Zero : PatLeaf<(imm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
628 int64_t Val = N->getSExtValue();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
629 return isInt<32>(Val) && !(Val & 0xffff);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
630 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
631
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
632 // shamt field must fit in 5 bits.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
633 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
634
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
635 // True if (N + 1) fits in 16-bit field.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
636 def immSExt16Plus1 : PatLeaf<(imm), [{
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
637 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
638 }]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
639
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
640 // Mips Address Mode! SDNode frameindex could possibily be a match
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
641 // since load and store instructions from stack used it.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
642 def addr :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
643 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
644
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
645 def addrRegImm :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
646 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
647
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
648 def addrRegReg :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
649 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
650
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
651 def addrDefault :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
652 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
653
|
|
77
|
654 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
|
|
|
655
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
656 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
657 // Instructions specific format
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
658 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
659
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
660 // Arithmetic and logical instructions with 3 register operands.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
661 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
662 InstrItinClass Itin = NoItinerary,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
663 SDPatternOperator OpNode = null_frag>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
664 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
665 !strconcat(opstr, "\t$rd, $rs, $rt"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
666 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
667 let isCommutable = isComm;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
668 let isReMaterializable = 1;
|
|
77
|
669 let TwoOperandAliasConstraint = "$rd = $rs";
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
670 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
671
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
672 // Arithmetic and logical instructions with 2 register operands.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
673 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
674 InstrItinClass Itin = NoItinerary,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
675 SDPatternOperator imm_type = null_frag,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
676 SDPatternOperator OpNode = null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
677 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
678 !strconcat(opstr, "\t$rt, $rs, $imm16"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
679 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
680 Itin, FrmI, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
681 let isReMaterializable = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
682 let TwoOperandAliasConstraint = "$rs = $rt";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
683 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
684
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
685 // Arithmetic Multiply ADD/SUB
|
|
77
|
686 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
687 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
|
77
|
688 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
689 let Defs = [HI0, LO0];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
690 let Uses = [HI0, LO0];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
691 let isCommutable = isComm;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
692 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
693
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
694 // Logical
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
695 class LogicNOR<string opstr, RegisterOperand RO>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
696 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
697 !strconcat(opstr, "\t$rd, $rs, $rt"),
|
|
77
|
698 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
699 let isCommutable = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
700 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
701
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
702 // Shifts
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
703 class shift_rotate_imm<string opstr, Operand ImmOpnd,
|
|
77
|
704 RegisterOperand RO, InstrItinClass itin,
|
|
|
705 SDPatternOperator OpNode = null_frag,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
706 SDPatternOperator PF = null_frag> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
707 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
708 !strconcat(opstr, "\t$rd, $rt, $shamt"),
|
|
77
|
709 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
|
|
|
710 let TwoOperandAliasConstraint = "$rt = $rd";
|
|
|
711 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
712
|
|
77
|
713 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
714 SDPatternOperator OpNode = null_frag>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
715 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
716 !strconcat(opstr, "\t$rd, $rt, $rs"),
|
|
77
|
717 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
|
|
|
718 opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
719
|
|
95
|
720 // Load Upper Immediate
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
721 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
722 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
|
|
77
|
723 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
|
|
83
|
724 let hasSideEffects = 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
725 let isReMaterializable = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
726 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
727
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
728 // Memory Load/Store
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
729 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
730 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
731 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
732 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
733 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
734 let canFoldAsLoad = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
735 let mayLoad = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
736 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
737
|
|
95
|
738 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
|
|
|
739 SDPatternOperator OpNode = null_frag,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
740 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
|
|
95
|
741 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
742 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
743 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
744 let mayStore = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
745 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
746
|
|
95
|
747 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
|
|
|
748 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
|
|
|
749 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
|
|
|
750
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
751 // Load/Store Left/Right
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
752 let canFoldAsLoad = 1 in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
753 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
754 InstrItinClass Itin> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
755 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
756 !strconcat(opstr, "\t$rt, $addr"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
757 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
758 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
759 string Constraints = "$src = $rt";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
760 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
761
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
762 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
763 InstrItinClass Itin> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
764 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
765 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
766 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
767 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
768
|
|
83
|
769 // COP2 Load/Store
|
|
|
770 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
|
|
771 SDPatternOperator OpNode= null_frag> :
|
|
|
772 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
|
|
773 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
|
|
|
774 let DecoderMethod = "DecodeFMem2";
|
|
|
775 let mayLoad = 1;
|
|
|
776 }
|
|
|
777
|
|
|
778 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
|
|
779 SDPatternOperator OpNode= null_frag> :
|
|
|
780 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
|
|
781 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
|
|
|
782 let DecoderMethod = "DecodeFMem2";
|
|
|
783 let mayStore = 1;
|
|
|
784 }
|
|
|
785
|
|
|
786 // COP3 Load/Store
|
|
|
787 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
|
|
788 SDPatternOperator OpNode= null_frag> :
|
|
|
789 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
|
|
790 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
|
|
|
791 let DecoderMethod = "DecodeFMem3";
|
|
|
792 let mayLoad = 1;
|
|
|
793 }
|
|
|
794
|
|
|
795 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
|
|
796 SDPatternOperator OpNode= null_frag> :
|
|
|
797 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
|
|
798 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
|
|
|
799 let DecoderMethod = "DecodeFMem3";
|
|
|
800 let mayStore = 1;
|
|
|
801 }
|
|
|
802
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
803 // Conditional Branch
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
804 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
|
|
83
|
805 RegisterOperand RO, bit DelaySlot = 1> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
806 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
807 !strconcat(opstr, "\t$rs, $rt, $offset"),
|
|
95
|
808 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
809 FrmI, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
810 let isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
811 let isTerminator = 1;
|
|
83
|
812 let hasDelaySlot = DelaySlot;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
813 let Defs = [AT];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
814 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
815
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
816 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
|
|
83
|
817 RegisterOperand RO, bit DelaySlot = 1> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
818 InstSE<(outs), (ins RO:$rs, opnd:$offset),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
819 !strconcat(opstr, "\t$rs, $offset"),
|
|
95
|
820 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
821 FrmI, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
822 let isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
823 let isTerminator = 1;
|
|
83
|
824 let hasDelaySlot = DelaySlot;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
825 let Defs = [AT];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
826 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
827
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
828 // SetCC
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
829 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
830 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
831 !strconcat(opstr, "\t$rd, $rs, $rt"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
832 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
|
|
77
|
833 II_SLT_SLTU, FrmR, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
834
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
835 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
836 RegisterOperand RO>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
837 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
838 !strconcat(opstr, "\t$rt, $rs, $imm16"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
839 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
|
|
77
|
840 II_SLTI_SLTIU, FrmI, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
841
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
842 // Jump
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
843 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
844 SDPatternOperator targetoperator, string bopstr> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
845 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
|
|
95
|
846 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
847 let isTerminator=1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
848 let isBarrier=1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
849 let hasDelaySlot = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
850 let DecoderMethod = "DecodeJumpTarget";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
851 let Defs = [AT];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
852 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
853
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
854 // Unconditional branch
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
855 class UncondBranch<Instruction BEQInst> :
|
|
95
|
856 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
857 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
858 let isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
859 let isTerminator = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
860 let isBarrier = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
861 let hasDelaySlot = 1;
|
|
77
|
862 let AdditionalPredicates = [RelocPIC];
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
863 let Defs = [AT];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
864 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
865
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
866 // Base class for indirect branch and return instruction classes.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
867 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
868 class JumpFR<string opstr, RegisterOperand RO,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
869 SDPatternOperator operator = null_frag>:
|
|
95
|
870 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
871 FrmR, opstr>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
872
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
873 // Indirect branch
|
|
77
|
874 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
875 let isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
876 let isIndirectBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
877 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
878
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
879 // Jump and Link (Call)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
880 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
881 class JumpLink<string opstr, DAGOperand opnd> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
882 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
|
|
95
|
883 [(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
884 let DecoderMethod = "DecodeJumpTarget";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
885 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
886
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
887 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
888 Register RetReg, RegisterOperand ResRO = RO>:
|
|
95
|
889 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
890 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
891
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
892 class JumpLinkReg<string opstr, RegisterOperand RO>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
893 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
|
95
|
894 [], II_JALR, FrmR, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
895
|
|
83
|
896 class BGEZAL_FT<string opstr, DAGOperand opnd,
|
|
|
897 RegisterOperand RO, bit DelaySlot = 1> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
898 InstSE<(outs), (ins RO:$rs, opnd:$offset),
|
|
95
|
899 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
|
|
83
|
900 let hasDelaySlot = DelaySlot;
|
|
|
901 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
902
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
903 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
904
|
|
33
|
905 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
|
|
|
906 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
|
|
|
907 class TailCall<Instruction JumpInst> :
|
|
95
|
908 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
|
|
33
|
909 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
|
|
|
910
|
|
|
911 class TailCallReg<RegisterOperand RO, Instruction JRInst,
|
|
|
912 RegisterOperand ResRO = RO> :
|
|
95
|
913 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
|
|
33
|
914 PseudoInstExpansion<(JRInst ResRO:$rs)>;
|
|
|
915 }
|
|
|
916
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
917 class BAL_BR_Pseudo<Instruction RealInst> :
|
|
95
|
918 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
919 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
920 let isBranch = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
921 let isTerminator = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
922 let isBarrier = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
923 let hasDelaySlot = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
924 let Defs = [RA];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
925 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
926
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
927 // Syscall
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
928 class SYS_FT<string opstr> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
929 InstSE<(outs), (ins uimm20:$code_),
|
|
77
|
930 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
931 // Break
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
932 class BRK_FT<string opstr> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
933 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
|
|
77
|
934 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
|
|
|
935 FrmOther, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
936
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
937 // (D)Eret
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
938 class ER_FT<string opstr> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
939 InstSE<(outs), (ins),
|
|
77
|
940 opstr, [], NoItinerary, FrmOther, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
941
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
942 // Interrupts
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
943 class DEI_FT<string opstr, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
944 InstSE<(outs RO:$rt), (ins),
|
|
77
|
945 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
946
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
947 // Wait
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
948 class WAIT_FT<string opstr> :
|
|
77
|
949 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
950
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
951 // Sync
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
952 let hasSideEffects = 1 in
|
|
77
|
953 class SYNC_FT<string opstr> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
954 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
|
|
77
|
955 NoItinerary, FrmOther, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
956
|
|
83
|
957 class SYNCI_FT<string opstr> :
|
|
|
958 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
|
|
|
959 NoItinerary, FrmOther, opstr> {
|
|
|
960 let hasSideEffects = 1;
|
|
|
961 let DecoderMethod = "DecodeSyncI";
|
|
|
962 }
|
|
|
963
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
964 let hasSideEffects = 1 in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
965 class TEQ_FT<string opstr, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
966 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
967 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
968 FrmI, opstr>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
969
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
970 class TEQI_FT<string opstr, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
971 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
972 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
973 // Mul, Div
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
974 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
975 list<Register> DefRegs> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
976 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
977 itin, FrmR, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
978 let isCommutable = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
979 let Defs = DefRegs;
|
|
83
|
980 let hasSideEffects = 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
981 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
982
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
983 // Pseudo multiply/divide instruction with explicit accumulator register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
984 // operands.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
985 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
986 SDPatternOperator OpNode, InstrItinClass Itin,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
987 bit IsComm = 1, bit HasSideEffects = 0,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
988 bit UsesCustomInserter = 0> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
989 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
990 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
991 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
992 let isCommutable = IsComm;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
993 let hasSideEffects = HasSideEffects;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
994 let usesCustomInserter = UsesCustomInserter;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
995 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
996
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
997 // Pseudo multiply add/sub instruction with explicit accumulator register
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
998 // operands.
|
|
77
|
999 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
|
|
|
1000 InstrItinClass itin>
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1001 : PseudoSE<(outs ACC64:$ac),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1002 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1003 [(set ACC64:$ac,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1004 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
|
|
77
|
1005 itin>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1006 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1007 string Constraints = "$acin = $ac";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1008 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1009
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1010 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1011 list<Register> DefRegs> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1012 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1013 [], itin, FrmR, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1014 let Defs = DefRegs;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1015 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1016
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1017 // Move from Hi/Lo
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1018 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1019 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
|
|
77
|
1020 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1021
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1022 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
|
|
77
|
1023 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
|
|
|
1024 FrmR, opstr> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1025 let Uses = [UseReg];
|
|
83
|
1026 let hasSideEffects = 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1027 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1028
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1029 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1030 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
|
|
77
|
1031 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
|
|
|
1032 II_MTHI_MTLO>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1033
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1034 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
|
|
77
|
1035 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1036 FrmR, opstr> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1037 let Defs = DefRegs;
|
|
83
|
1038 let hasSideEffects = 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1039 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1040
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1041 class EffectiveAddress<string opstr, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1042 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
|
77
|
1043 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
|
|
|
1044 !strconcat(opstr, "_lea")> {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1045 let isCodeGenOnly = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1046 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1047 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1048
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1049 // Count Leading Ones/Zeros in Word
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1050 class CountLeading0<string opstr, RegisterOperand RO>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1051 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
|
77
|
1052 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1053
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1054 class CountLeading1<string opstr, RegisterOperand RO>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1055 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
|
77
|
1056 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1057
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1058 // Sign Extend in Register.
|
|
77
|
1059 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
|
|
|
1060 InstrItinClass itin> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1061 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
|
|
77
|
1062 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1063
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1064 // Subword Swap
|
|
95
|
1065 class SubwordSwap<string opstr, RegisterOperand RO,
|
|
|
1066 InstrItinClass itin = NoItinerary>:
|
|
|
1067 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
|
|
|
1068 FrmR, opstr> {
|
|
83
|
1069 let hasSideEffects = 0;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1070 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1071
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1072 // Read Hardware
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1073 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1074 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
|
|
83
|
1075 II_RDHWR, FrmR, "rdhwr">;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1076
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1077 // Ext and Ins
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1078 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1079 SDPatternOperator Op = null_frag>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1080 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1081 !strconcat(opstr, " $rt, $rs, $pos, $size"),
|
|
95
|
1082 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
|
|
77
|
1083 FrmR, opstr>, ISA_MIPS32R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1084
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1085 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1086 SDPatternOperator Op = null_frag>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1087 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1088 !strconcat(opstr, " $rt, $rs, $pos, $size"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1089 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
|
|
95
|
1090 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1091 let Constraints = "$src = $rt";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1092 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1093
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1094 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1095 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1096 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1097 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1098
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1099 // Atomic Compare & Swap.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1100 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1101 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1102 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1103
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1104 class LLBase<string opstr, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1105 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1106 [], NoItinerary, FrmI> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1107 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1108 let mayLoad = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1109 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1110
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1111 class SCBase<string opstr, RegisterOperand RO> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1112 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1113 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1114 let DecoderMethod = "DecodeMem";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1115 let mayStore = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1116 let Constraints = "$rt = $dst";
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1117 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1118
|
|
95
|
1119 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
|
|
|
1120 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
|
|
|
1121 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
|
|
|
1122
|
|
|
1123 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
|
|
|
1124 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1125 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1126
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1127 class TrapBase<Instruction RealInst>
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1128 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1129 PseudoInstExpansion<(RealInst 0, 0)> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1130 let isBarrier = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1131 let isTerminator = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1132 let isCodeGenOnly = 1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1133 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1134
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1135 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1136 // Pseudo instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1137 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1138
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1139 // Return RA.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1140 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1141 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1142
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1143 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1144 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1145 [(callseq_start timm:$amt)]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1146 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1147 [(callseq_end timm:$amt1, timm:$amt2)]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1148 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1149
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1150 let usesCustomInserter = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1151 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1152 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1153 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1154 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1155 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1156 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1157 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1158 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1159 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1160 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1161 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1162 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1163 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1164 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1165 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1166 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1167 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1168 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1169
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1170 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1171 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1172 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1173
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1174 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1175 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1176 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1177 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1178
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1179 /// Pseudo instructions for loading and storing accumulator registers.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1180 let isPseudo = 1, isCodeGenOnly = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1181 def LOAD_ACC64 : Load<"", ACC64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1182 def STORE_ACC64 : Store<"", ACC64>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1183 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1184
|
|
77
|
1185 // We need these two pseudo instructions to avoid offset calculation for long
|
|
|
1186 // branches. See the comment in file MipsLongBranch.cpp for detailed
|
|
|
1187 // explanation.
|
|
|
1188
|
|
|
1189 // Expands to: lui $dst, %hi($tgt - $baltgt)
|
|
|
1190 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
|
|
|
1191 (ins brtarget:$tgt, brtarget:$baltgt), []>;
|
|
|
1192
|
|
|
1193 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
|
|
|
1194 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
|
|
|
1195 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
|
|
|
1196
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1197 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1198 // Instruction definition
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1199 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1200 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1201 // MipsI Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1202 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1203
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1204 /// Arithmetic Instructions (ALU Immediate)
|
|
83
|
1205 let AdditionalPredicates = [NotInMicroMips] in {
|
|
95
|
1206 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
|
|
|
1207 II_ADDIU, immSExt16, add>,
|
|
|
1208 ADDI_FM<0x9>, IsAsCheapAsAMove;
|
|
83
|
1209 }
|
|
77
|
1210 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
|
|
|
1211 ISA_MIPS1_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1212 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1213 SLTI_FM<0xa>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1214 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1215 SLTI_FM<0xb>;
|
|
83
|
1216 let AdditionalPredicates = [NotInMicroMips] in {
|
|
95
|
1217 def ANDi : MMRel, StdMMR6Rel,
|
|
|
1218 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
|
|
|
1219 ADDI_FM<0xc>;
|
|
83
|
1220 }
|
|
95
|
1221 def ORi : MMRel, StdMMR6Rel,
|
|
|
1222 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1223 ADDI_FM<0xd>;
|
|
95
|
1224 def XORi : MMRel, StdMMR6Rel,
|
|
|
1225 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1226 ADDI_FM<0xe>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1227 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
|
|
95
|
1228 let AdditionalPredicates = [NotInMicroMips] in {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1229 /// Arithmetic Instructions (3-Operand, R-Type)
|
|
95
|
1230 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1231 ADD_FM<0, 0x21>;
|
|
77
|
1232 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1233 ADD_FM<0, 0x23>;
|
|
95
|
1234 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1235 let Defs = [HI0, LO0] in
|
|
77
|
1236 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
|
|
|
1237 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
|
|
95
|
1238 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1239 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1240 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1241 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
|
|
95
|
1242 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1243 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1244 ADD_FM<0, 0x24>;
|
|
95
|
1245 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1246 ADD_FM<0, 0x25>;
|
|
95
|
1247 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1248 ADD_FM<0, 0x26>;
|
|
95
|
1249 }
|
|
|
1250 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1251
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1252 /// Shift Instructions
|
|
83
|
1253 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
1254 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
|
|
|
1255 immZExt5>, SRA_FM<0, 0>;
|
|
|
1256 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
|
|
|
1257 immZExt5>, SRA_FM<2, 0>;
|
|
83
|
1258 }
|
|
77
|
1259 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
|
|
|
1260 immZExt5>, SRA_FM<3, 0>;
|
|
|
1261 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
|
|
|
1262 SRLV_FM<4, 0>;
|
|
|
1263 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
|
|
|
1264 SRLV_FM<6, 0>;
|
|
|
1265 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
|
|
|
1266 SRLV_FM<7, 0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1267
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1268 // Rotate Instructions
|
|
77
|
1269 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
|
|
|
1270 immZExt5>,
|
|
|
1271 SRA_FM<2, 1>, ISA_MIPS32R2;
|
|
|
1272 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
|
|
|
1273 SRLV_FM<6, 1>, ISA_MIPS32R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1274
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1275 /// Load and Store Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1276 /// aligned
|
|
77
|
1277 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
|
|
|
1278 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1279 LW_FM<0x24>;
|
|
77
|
1280 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1281 LW_FM<0x21>;
|
|
77
|
1282 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
|
|
83
|
1283 let AdditionalPredicates = [NotInMicroMips] in {
|
|
95
|
1284 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1285 LW_FM<0x23>;
|
|
83
|
1286 }
|
|
95
|
1287 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
|
|
|
1288 LW_FM<0x28>;
|
|
77
|
1289 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
|
|
83
|
1290 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
1291 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
|
|
83
|
1292 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1293
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1294 /// load/store left/right
|
|
77
|
1295 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
|
|
1296 AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1297 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
|
|
|
1298 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1299 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
|
|
|
1300 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1301 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
|
|
|
1302 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1303 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
|
|
|
1304 ISA_MIPS1_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1305 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1306
|
|
83
|
1307 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1308 // COP2 Memory Instructions
|
|
|
1309 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
|
|
|
1310 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1311 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
|
|
|
1312 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1313 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
|
|
|
1314 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1315 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
|
|
|
1316 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1317
|
|
|
1318 // COP3 Memory Instructions
|
|
|
1319 let DecoderNamespace = "COP3_" in {
|
|
|
1320 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
|
|
|
1321 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
|
|
|
1322 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
|
|
|
1323 ISA_MIPS2;
|
|
|
1324 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
|
|
|
1325 ISA_MIPS2;
|
|
|
1326 }
|
|
|
1327 }
|
|
|
1328
|
|
77
|
1329 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
|
|
83
|
1330 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
|
|
77
|
1331
|
|
95
|
1332 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1333 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
|
|
|
1334 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
|
|
|
1335 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
|
|
|
1336 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
|
|
|
1337 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
|
|
|
1338 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
|
|
|
1339 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1340
|
|
77
|
1341 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
|
|
|
1342 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1343 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
|
|
|
1344 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1345 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
|
|
|
1346 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1347 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
|
|
|
1348 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1349 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
|
|
|
1350 ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1351 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
|
|
|
1352 ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1353
|
|
95
|
1354 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1355 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
|
|
|
1356 }
|
|
77
|
1357 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1358 def TRAP : TrapBase<BREAK>;
|
|
83
|
1359 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1360
|
|
95
|
1361 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1362 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
|
|
|
1363 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
|
|
|
1364 }
|
|
|
1365 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1366
|
|
95
|
1367 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1368 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
|
|
|
1369 }
|
|
77
|
1370 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1371
|
|
77
|
1372 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
|
|
1373 AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1374 def WAIT : WAIT_FT<"wait">, WAIT_FM;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1375
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1376 /// Load-linked, Store-conditional
|
|
77
|
1377 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1378 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1379 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1380
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1381 /// Jump and Branch Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1382 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
|
|
77
|
1383 AdditionalRequires<[RelocStatic]>, IsBranch;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1384 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1385 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
|
|
83
|
1386 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
|
|
|
1387 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1388 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
|
|
83
|
1389 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
|
|
|
1390 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1391 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1392 BGEZ_FM<1, 1>;
|
|
83
|
1393 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
|
|
|
1394 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1395 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1396 BGEZ_FM<7, 0>;
|
|
83
|
1397 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
|
|
|
1398 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1399 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1400 BGEZ_FM<6, 0>;
|
|
83
|
1401 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
|
|
|
1402 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1403 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1404 BGEZ_FM<1, 0>;
|
|
83
|
1405 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
|
|
|
1406 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1407 def B : UncondBranch<BEQ>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1408
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1409 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
|
|
77
|
1410 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1411 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
|
|
|
1412 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
|
|
|
1413 }
|
|
|
1414
|
|
95
|
1415 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
|
|
|
1416 ISA_MIPS32_NOT_32R6_64R6;
|
|
77
|
1417 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
|
|
|
1418 ISA_MIPS1_NOT_32R6_64R6;
|
|
83
|
1419 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
|
|
|
1420 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
|
|
77
|
1421 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
|
|
|
1422 ISA_MIPS1_NOT_32R6_64R6;
|
|
83
|
1423 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
|
|
|
1424 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1425 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
|
|
33
|
1426 def TAILCALL : TailCall<J>;
|
|
|
1427 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1428
|
|
77
|
1429 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
|
|
|
1430 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
|
|
|
1431 class PseudoIndirectBranchBase<RegisterOperand RO> :
|
|
95
|
1432 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
|
|
|
1433 II_IndirectBranchPseudo> {
|
|
77
|
1434 let isTerminator=1;
|
|
|
1435 let isBarrier=1;
|
|
|
1436 let hasDelaySlot = 1;
|
|
|
1437 let isBranch = 1;
|
|
|
1438 let isIndirectBranch = 1;
|
|
|
1439 }
|
|
|
1440
|
|
|
1441 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
|
|
|
1442
|
|
95
|
1443 // Return instructions are matched as a RetRA instruction, then are expanded
|
|
77
|
1444 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
|
|
|
1445 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
|
|
|
1446 // ISA.
|
|
|
1447 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
|
|
95
|
1448 [], II_ReturnPseudo> {
|
|
77
|
1449 let isTerminator = 1;
|
|
|
1450 let isBarrier = 1;
|
|
|
1451 let hasDelaySlot = 1;
|
|
|
1452 let isReturn = 1;
|
|
|
1453 let isCodeGenOnly = 1;
|
|
|
1454 let hasCtrlDep = 1;
|
|
|
1455 let hasExtraSrcRegAllocReq = 1;
|
|
|
1456 }
|
|
|
1457
|
|
|
1458 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1459
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1460 // Exception handling related node and instructions.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1461 // The conversion sequence is:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1462 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1463 // MIPSeh_return -> (stack change + indirect branch)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1464 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1465 // MIPSeh_return takes the place of regular return instruction
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1466 // but takes two arguments (V1, V0) which are used for storing
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1467 // the offset and return address respectively.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1468 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1469
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1470 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1471 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1472
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1473 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1474 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1475 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1476 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1477 GPR64:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1478 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1479 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1480
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1481 /// Multiply and Divide Instructions.
|
|
77
|
1482 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
|
|
|
1483 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1484 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
|
|
|
1485 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1486 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
|
|
|
1487 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1488 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
|
|
|
1489 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1490
|
|
77
|
1491 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
|
|
|
1492 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1493 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
|
|
|
1494 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1495 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
|
|
1496 AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1497 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
|
|
|
1498 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1499 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
|
|
|
1500 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1501 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1502
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1503 /// Sign Ext In Register Instructions.
|
|
95
|
1504 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
|
|
77
|
1505 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
|
|
95
|
1506 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
|
|
77
|
1507 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1508
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1509 /// Count Leading
|
|
77
|
1510 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
|
|
|
1511 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1512 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
|
|
|
1513 ISA_MIPS32_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1514
|
|
95
|
1515 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1516 /// Word Swap Bytes Within Halfwords
|
|
|
1517 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
|
|
|
1518 ISA_MIPS32R2;
|
|
|
1519 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1520
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1521 /// No operation.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1522 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1523
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1524 // FrameIndexes are legalized when they are operands from load/store
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1525 // instructions. The same not happens for stack address copies, so an
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1526 // add op with mem ComplexPattern is used and the stack address copy
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1527 // can be matched. It's similar to Sparc LEA_ADDRi
|
|
77
|
1528 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1529
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1530 // MADD*/MSUB*
|
|
77
|
1531 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
|
|
|
1532 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1533 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
|
|
|
1534 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1535 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
|
|
|
1536 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1537 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
|
|
|
1538 ISA_MIPS32_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1539
|
|
77
|
1540 let AdditionalPredicates = [NotDSP] in {
|
|
|
1541 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
|
|
|
1542 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1543 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
|
|
|
1544 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1545 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1546 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1547 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1548 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
|
|
|
1549 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1550 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
|
|
|
1551 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1552 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
|
|
|
1553 ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1554 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
|
|
|
1555 ISA_MIPS32_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1556 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1557
|
|
77
|
1558 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
|
|
|
1559 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1560 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
|
|
|
1561 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1562
|
|
83
|
1563 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1564
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1565 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1566 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1567
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1568 /// Move Control Registers From/To CPU Registers
|
|
95
|
1569 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
|
|
|
1570 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
|
|
|
1571 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
|
|
|
1572 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1573
|
|
77
|
1574 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
|
|
83
|
1575 FrmOther, asmstr>;
|
|
|
1576 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
|
|
|
1577 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
|
|
|
1578 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
|
|
77
|
1579
|
|
|
1580 // JR_HB and JALR_HB are defined here using the new style naming
|
|
|
1581 // scheme because some of this code is shared with Mips32r6InstrInfo.td
|
|
|
1582 // and because of that it doesn't follow the naming convention of the
|
|
|
1583 // rest of the file. To avoid a mixture of old vs new style, the new
|
|
|
1584 // style was chosen.
|
|
|
1585 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
|
|
|
1586 dag OutOperandList = (outs);
|
|
|
1587 dag InOperandList = (ins GPROpnd:$rs);
|
|
|
1588 string AsmString = !strconcat(instr_asm, "\t$rs");
|
|
|
1589 list<dag> Pattern = [];
|
|
|
1590 }
|
|
|
1591
|
|
|
1592 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
|
|
|
1593 dag OutOperandList = (outs GPROpnd:$rd);
|
|
|
1594 dag InOperandList = (ins GPROpnd:$rs);
|
|
|
1595 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
|
|
|
1596 list<dag> Pattern = [];
|
|
|
1597 }
|
|
|
1598
|
|
|
1599 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
|
|
|
1600 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
|
|
|
1601 let isBranch=1;
|
|
|
1602 let isIndirectBranch=1;
|
|
|
1603 let hasDelaySlot=1;
|
|
|
1604 let isTerminator=1;
|
|
|
1605 let isBarrier=1;
|
|
|
1606 }
|
|
|
1607
|
|
|
1608 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
|
|
|
1609 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
|
|
|
1610 let isIndirectBranch=1;
|
|
|
1611 let hasDelaySlot=1;
|
|
|
1612 }
|
|
|
1613
|
|
|
1614 class JR_HB_ENC : JR_HB_FM<8>;
|
|
|
1615 class JALR_HB_ENC : JALR_HB_FM<9>;
|
|
|
1616
|
|
|
1617 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1618 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
|
|
|
1619
|
|
|
1620 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
|
|
83
|
1621 FrmOther, asmstr>;
|
|
|
1622 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
|
|
|
1623 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
|
|
|
1624 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
|
|
|
1625 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
|
|
77
|
1626
|
|
83
|
1627 class CacheOp<string instr_asm, Operand MemOpnd> :
|
|
77
|
1628 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
|
|
83
|
1629 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
|
|
|
1630 instr_asm> {
|
|
|
1631 let DecoderMethod = "DecodeCacheOp";
|
|
|
1632 }
|
|
77
|
1633
|
|
83
|
1634 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
|
|
77
|
1635 INSN_MIPS3_32_NOT_32R6_64R6;
|
|
83
|
1636 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
|
|
77
|
1637 INSN_MIPS3_32_NOT_32R6_64R6;
|
|
|
1638
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1639 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1640 // Instruction aliases
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1641 //===----------------------------------------------------------------------===//
|
|
77
|
1642 def : MipsInstAlias<"move $dst, $src",
|
|
95
|
1643 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
|
|
|
1644 GPR_32 {
|
|
|
1645 let AdditionalPredicates = [NotInMicroMips];
|
|
|
1646 }
|
|
|
1647 def : MipsInstAlias<"move $dst, $src",
|
|
|
1648 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
|
|
77
|
1649 GPR_32 {
|
|
|
1650 let AdditionalPredicates = [NotInMicroMips];
|
|
|
1651 }
|
|
|
1652 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
|
|
|
1653 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1654 def : MipsInstAlias<"addu $rs, $rt, $imm",
|
|
|
1655 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
|
|
83
|
1656 def : MipsInstAlias<"addu $rs, $imm",
|
|
|
1657 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
|
|
77
|
1658 def : MipsInstAlias<"add $rs, $rt, $imm",
|
|
83
|
1659 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
|
|
|
1660 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1661 def : MipsInstAlias<"add $rs, $imm",
|
|
|
1662 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
|
|
|
1663 ISA_MIPS1_NOT_32R6_64R6;
|
|
77
|
1664 def : MipsInstAlias<"and $rs, $rt, $imm",
|
|
|
1665 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
|
|
|
1666 def : MipsInstAlias<"and $rs, $imm",
|
|
|
1667 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
|
|
|
1668 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
|
|
|
1669 let Predicates = [NotInMicroMips] in {
|
|
|
1670 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
|
|
|
1671 }
|
|
|
1672 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
|
|
|
1673 def : MipsInstAlias<"not $rt, $rs",
|
|
|
1674 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
|
|
|
1675 def : MipsInstAlias<"neg $rt, $rs",
|
|
|
1676 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
|
|
|
1677 def : MipsInstAlias<"negu $rt",
|
|
|
1678 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
|
|
|
1679 def : MipsInstAlias<"negu $rt, $rs",
|
|
|
1680 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
|
|
|
1681 def : MipsInstAlias<"slt $rs, $rt, $imm",
|
|
|
1682 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
|
|
|
1683 def : MipsInstAlias<"sltu $rt, $rs, $imm",
|
|
|
1684 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
|
|
|
1685 def : MipsInstAlias<"xor $rs, $rt, $imm",
|
|
|
1686 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
|
|
95
|
1687 def : MipsInstAlias<"xor $rs, $imm",
|
|
|
1688 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
|
|
77
|
1689 def : MipsInstAlias<"or $rs, $rt, $imm",
|
|
|
1690 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
|
|
|
1691 def : MipsInstAlias<"or $rs, $imm",
|
|
|
1692 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
|
|
95
|
1693 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
1694 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
|
|
95
|
1695 }
|
|
|
1696 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
|
|
|
1697 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
|
|
|
1698 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
|
|
|
1699 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
|
|
83
|
1700 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
1701 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
|
|
83
|
1702 }
|
|
77
|
1703 def : MipsInstAlias<"bnez $rs,$offset",
|
|
|
1704 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
|
95
|
1705 def : MipsInstAlias<"bnezl $rs,$offset",
|
|
|
1706 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
|
77
|
1707 def : MipsInstAlias<"beqz $rs,$offset",
|
|
|
1708 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
|
95
|
1709 def : MipsInstAlias<"beqzl $rs,$offset",
|
|
|
1710 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
|
77
|
1711 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
|
|
95
|
1712
|
|
77
|
1713 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
|
|
|
1714 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
|
|
95
|
1715 let AdditionalPredicates = [NotInMicroMips] in {
|
|
83
|
1716 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
|
|
95
|
1717 }
|
|
83
|
1718 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
|
|
95
|
1719 let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
1720 def : MipsInstAlias<"teq $rs, $rt",
|
|
|
1721 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|
|
|
1722 def : MipsInstAlias<"tge $rs, $rt",
|
|
|
1723 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|
|
|
1724 def : MipsInstAlias<"tgeu $rs, $rt",
|
|
|
1725 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|
|
|
1726 def : MipsInstAlias<"tlt $rs, $rt",
|
|
|
1727 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|
|
|
1728 def : MipsInstAlias<"tltu $rs, $rt",
|
|
|
1729 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|
|
|
1730 def : MipsInstAlias<"tne $rs, $rt",
|
|
|
1731 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|
|
|
1732 }
|
|
77
|
1733 def : MipsInstAlias<"sll $rd, $rt, $rs",
|
|
|
1734 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
|
1735 def : MipsInstAlias<"sub, $rd, $rs, $imm",
|
|
|
1736 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
|
|
83
|
1737 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
|
|
77
|
1738 def : MipsInstAlias<"sub $rs, $imm",
|
|
|
1739 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
|
|
83
|
1740 0>, ISA_MIPS1_NOT_32R6_64R6;
|
|
77
|
1741 def : MipsInstAlias<"subu, $rd, $rs, $imm",
|
|
|
1742 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
|
|
|
1743 InvertedImOperand:$imm), 0>;
|
|
|
1744 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
|
|
|
1745 InvertedImOperand:$imm), 0>;
|
|
|
1746 def : MipsInstAlias<"sra $rd, $rt, $rs",
|
|
|
1747 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
|
1748 def : MipsInstAlias<"srl $rd, $rt, $rs",
|
|
|
1749 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
|
1750 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
|
|
|
1751 def : MipsInstAlias<"sync",
|
|
|
1752 (SYNC 0), 1>, ISA_MIPS2;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1753 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1754 // Assembler Pseudo Instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1755 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1756
|
|
95
|
1757 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1758 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1759 !strconcat(instr_asm, "\t$rt, $imm32")> ;
|
|
95
|
1760 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1761
|
|
95
|
1762 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
|
|
|
1763 RegisterOperand RO> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1764 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1765 !strconcat(instr_asm, "\t$rt, $addr")> ;
|
|
95
|
1766 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1767
|
|
95
|
1768 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1769 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1770 !strconcat(instr_asm, "\t$rt, $imm32")> ;
|
|
95
|
1771 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1772
|
|
83
|
1773 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
|
|
|
1774 "jal\t$rd, $rs"> ;
|
|
|
1775 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
|
|
|
1776 "jal\t$rs"> ;
|
|
|
1777
|
|
95
|
1778 def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
|
|
|
1779 "nor\t$rs, $rt, $imm"> ;
|
|
|
1780
|
|
|
1781 let hasDelaySlot = 1 in {
|
|
|
1782 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
|
|
|
1783 (ins imm64:$imm64, brtarget:$offset),
|
|
|
1784 "bne\t$rt, $imm64, $offset">;
|
|
|
1785 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
|
|
|
1786 (ins imm64:$imm64, brtarget:$offset),
|
|
|
1787 "beq\t$rt, $imm64, $offset">;
|
|
|
1788
|
|
|
1789 class CondBranchPseudo<string instr_asm> :
|
|
|
1790 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
|
|
|
1791 brtarget:$offset),
|
|
|
1792 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
|
|
|
1793 }
|
|
|
1794
|
|
|
1795 def BLT : CondBranchPseudo<"blt">;
|
|
|
1796 def BLE : CondBranchPseudo<"ble">;
|
|
|
1797 def BGE : CondBranchPseudo<"bge">;
|
|
|
1798 def BGT : CondBranchPseudo<"bgt">;
|
|
|
1799 def BLTU : CondBranchPseudo<"bltu">;
|
|
|
1800 def BLEU : CondBranchPseudo<"bleu">;
|
|
|
1801 def BGEU : CondBranchPseudo<"bgeu">;
|
|
|
1802 def BGTU : CondBranchPseudo<"bgtu">;
|
|
|
1803 def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1804 def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1805 def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1806 def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1807 def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1808 def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1809 def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1810 def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1811
|
|
|
1812 class CondBranchImmPseudo<string instr_asm> :
|
|
|
1813 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
|
|
|
1814 !strconcat(instr_asm, "\t$rs, $imm, $offset")>;
|
|
|
1815
|
|
|
1816 def BLTImmMacro : CondBranchImmPseudo<"blt">;
|
|
|
1817 def BLEImmMacro : CondBranchImmPseudo<"ble">;
|
|
|
1818 def BGEImmMacro : CondBranchImmPseudo<"bge">;
|
|
|
1819 def BGTImmMacro : CondBranchImmPseudo<"bgt">;
|
|
|
1820 def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
|
|
|
1821 def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
|
|
|
1822 def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
|
|
|
1823 def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;
|
|
|
1824 def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1825 def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1826 def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1827 def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1828 def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1829 def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1830 def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1831 def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
|
|
|
1832
|
|
|
1833 // FIXME: Predicates are removed because instructions are matched regardless of
|
|
|
1834 // predicates, because PredicateControl was not in the hierarchy. This was
|
|
|
1835 // done to emit more precise error message from expansion function.
|
|
|
1836 // Once the tablegen-erated errors are made better, this needs to be fixed and
|
|
|
1837 // predicates needs to be restored.
|
|
|
1838
|
|
|
1839 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
|
|
1840 "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1841
|
|
|
1842 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
|
|
1843 "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1844
|
|
|
1845 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
|
|
1846 "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
|
|
|
1847
|
|
|
1848 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
|
|
1849 "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
|
|
|
1850
|
|
|
1851 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
|
|
|
1852 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1853
|
|
|
1854 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
|
|
|
1855 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1856
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1857 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1858 // Arbitrary patterns that map to one or more instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1859 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1860
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1861 // Load/store pattern templates.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1862 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1863 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1864
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1865 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1866 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1867
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1868 // Small immediates
|
|
83
|
1869 let AdditionalPredicates = [NotInMicroMips] in {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1870 def : MipsPat<(i32 immSExt16:$in),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1871 (ADDiu ZERO, imm:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1872 def : MipsPat<(i32 immZExt16:$in),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1873 (ORi ZERO, imm:$in)>;
|
|
83
|
1874 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1875 def : MipsPat<(i32 immLow16Zero:$in),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1876 (LUi (HI16 imm:$in))>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1877
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1878 // Arbitrary immediates
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1879 def : MipsPat<(i32 imm:$imm),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1880 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1881
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1882 // Carry MipsPatterns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1883 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1884 (SUBu GPR32:$lhs, GPR32:$rhs)>;
|
|
77
|
1885 let AdditionalPredicates = [NotDSP] in {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1886 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1887 (ADDu GPR32:$lhs, GPR32:$rhs)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1888 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1889 (ADDiu GPR32:$src, imm:$imm)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1890 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1891
|
|
83
|
1892 // Support multiplication for pre-Mips32 targets that don't have
|
|
|
1893 // the MUL instruction.
|
|
|
1894 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
|
|
|
1895 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
|
|
|
1896 ISA_MIPS1_NOT_32R6_64R6;
|
|
|
1897
|
|
77
|
1898 // SYNC
|
|
|
1899 def : MipsPat<(MipsSync (i32 immz)),
|
|
|
1900 (SYNC 0)>, ISA_MIPS2;
|
|
|
1901
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1902 // Call
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1903 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1904 (JAL tglobaladdr:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1905 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1906 (JAL texternalsym:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1907 //def : MipsPat<(MipsJmpLink GPR32:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1908 // (JALR GPR32:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1909
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1910 // Tail call
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1911 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1912 (TAILCALL tglobaladdr:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1913 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1914 (TAILCALL texternalsym:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1915 // hi/lo relocs
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1916 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1917 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1918 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1919 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1920 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1921 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1922
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1923 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1924 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1925 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1926 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1927 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1928 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1929
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1930 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1931 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1932 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1933 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1934 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1935 (ADDiu GPR32:$hi, tjumptable:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1936 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1937 (ADDiu GPR32:$hi, tconstpool:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1938 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1939 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1940
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1941 // gp_rel relocs
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1942 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1943 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1944 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1945 (ADDiu GPR32:$gp, tconstpool:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1946
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1947 // wrapper_pic
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1948 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1949 MipsPat<(MipsWrapper RC:$gp, node:$in),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1950 (ADDiuOp RC:$gp, node:$in)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1951
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1952 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1953 def : WrapperPat<tconstpool, ADDiu, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1954 def : WrapperPat<texternalsym, ADDiu, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1955 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1956 def : WrapperPat<tjumptable, ADDiu, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1957 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1958
|
|
95
|
1959 let AdditionalPredicates = [NotInMicroMips] in {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1960 // Mips does not have "not", so we expand our way
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1961 def : MipsPat<(not GPR32:$in),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1962 (NOR GPR32Opnd:$in, ZERO)>;
|
|
95
|
1963 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1964
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1965 // extended loads
|
|
77
|
1966 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
|
|
1967 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
|
|
1968 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1969
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1970 // peepholes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1971 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1972
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1973 // brcond patterns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1974 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1975 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1976 Instruction SLTiuOp, Register ZEROReg> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1977 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1978 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1979 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1980 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1981
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1982 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1983 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1984 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1985 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1986 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1987 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1988 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1989 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1990 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1991 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1992 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1993 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1994
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1995 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1996 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1997 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1998 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1999
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2000 def : MipsPat<(brcond RC:$cond, bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2001 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2002 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2003
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2004 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2005
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2006 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2007 (BLEZ i32:$lhs, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2008 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2009 (BGEZ i32:$lhs, bb:$dst)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2010
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2011 // setcc patterns
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2012 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2013 Instruction SLTuOp, Register ZEROReg> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2014 def : MipsPat<(seteq RC:$lhs, 0),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2015 (SLTiuOp RC:$lhs, 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2016 def : MipsPat<(setne RC:$lhs, 0),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2017 (SLTuOp ZEROReg, RC:$lhs)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2018 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2019 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2020 def : MipsPat<(setne RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2021 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2022 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2023
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2024 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2025 def : MipsPat<(setle RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2026 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2027 def : MipsPat<(setule RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2028 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2029 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2030
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2031 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2032 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2033 (SLTOp RC:$rhs, RC:$lhs)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2034 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2035 (SLTuOp RC:$rhs, RC:$lhs)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2036 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2037
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2038 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2039 def : MipsPat<(setge RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2040 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2041 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2042 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2043 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2044
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2045 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2046 Instruction SLTiuOp> {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2047 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2048 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2049 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2050 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2051 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2052
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2053 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2054 defm : SetlePats<GPR32, SLT, SLTu>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2055 defm : SetgtPats<GPR32, SLT, SLTu>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2056 defm : SetgePats<GPR32, SLT, SLTu>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2057 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2058
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2059 // bswap pattern
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2060 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2061
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2062 // Load halfword/word patterns.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2063 let AddedComplexity = 40 in {
|
|
77
|
2064 def : LoadRegImmPat<LBu, i32, zextloadi8>;
|
|
|
2065 def : LoadRegImmPat<LH, i32, sextloadi16>;
|
|
83
|
2066 let AdditionalPredicates = [NotInMicroMips] in {
|
|
77
|
2067 def : LoadRegImmPat<LW, i32, load>;
|
|
83
|
2068 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2069 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2070
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2071 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2072 // Floating Point Support
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2073 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2074
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2075 include "MipsInstrFPU.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2076 include "Mips64InstrInfo.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2077 include "MipsCondMov.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2078
|
|
77
|
2079 include "Mips32r6InstrInfo.td"
|
|
|
2080 include "Mips64r6InstrInfo.td"
|
|
|
2081
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2082 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2083 // Mips16
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2084
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2085 include "Mips16InstrFormats.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2086 include "Mips16InstrInfo.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2087
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2088 // DSP
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2089 include "MipsDSPInstrFormats.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2090 include "MipsDSPInstrInfo.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2091
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2092 // MSA
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2093 include "MipsMSAInstrFormats.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2094 include "MipsMSAInstrInfo.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2095
|
|
95
|
2096 // EVA
|
|
|
2097 include "MipsEVAInstrFormats.td"
|
|
|
2098 include "MipsEVAInstrInfo.td"
|
|
|
2099
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2100 // Micromips
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2101 include "MicroMipsInstrFormats.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
2102 include "MicroMipsInstrInfo.td"
|
|
77
|
2103 include "MicroMipsInstrFPU.td"
|
|
95
|
2104
|
|
|
2105 // Micromips r6
|
|
|
2106 include "MicroMips32r6InstrFormats.td"
|
|
|
2107 include "MicroMips32r6InstrInfo.td"
|
|
|
2108
|
|
|
2109 // Micromips64 r6
|
|
|
2110 include "MicroMips64r6InstrFormats.td"
|
|
|
2111 include "MicroMips64r6InstrInfo.td"
|
|
|
2112
|
|
|
2113 // Micromips DSP
|
|
|
2114 include "MicroMipsDSPInstrFormats.td"
|
|
|
2115 include "MicroMipsDSPInstrInfo.td"
|
