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comparison lib/Target/Hexagon/HexagonScheduleV62.td @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 803732b1fca8
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134:3a76565eade5 147:c2174574ed3a
1 //=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=// 1 //=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // ScalarItin contains some old itineraries still used by a 9 // ScalarItin contains some old itineraries still used by a
11 // handful of instructions. Hopefully, we will be able to get rid of them soon. 10 // handful of instructions. Hopefully, we will be able to get rid of them soon.
19 18
20 def HexagonItinerariesV62 : 19 def HexagonItinerariesV62 :
21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, 20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
22 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, 21 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
23 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, 22 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
24 CVI_ALL_NOMEM], 23 CVI_ALL_NOMEM, CVI_ZW],
25 [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>; 24 [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>;
26 25
27 def HexagonModelV62 : SchedMachineModel { 26 def HexagonModelV62 : SchedMachineModel {
28 // Max issue per cycle == bundle width. 27 // Max issue per cycle == bundle width.
29 let IssueWidth = 4; 28 let IssueWidth = 4;