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1 //=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // ScalarItin contains some old itineraries still used by a
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10 // handful of instructions. Hopefully, we will be able to get rid of them soon.
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11
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12 def HexagonV62ItinList : DepScalarItinV62, ScalarItin,
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13 DepHVXItinV62, HVXItin, PseudoItin {
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14 list<InstrItinData> ItinList =
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15 !listconcat(DepScalarItinV62_list, ScalarItin_list,
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16 DepHVXItinV62_list, HVXItin_list, PseudoItin_list);
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17 }
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18
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19 def HexagonItinerariesV62 :
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20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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21 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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22 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
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23 CVI_ALL_NOMEM, CVI_ZW],
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24 [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>;
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25
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26 def HexagonModelV62 : SchedMachineModel {
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27 // Max issue per cycle == bundle width.
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28 let IssueWidth = 4;
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29 let Itineraries = HexagonItinerariesV62;
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30 let LoadLatency = 1;
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31 let CompleteModel = 0;
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32 }
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33
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34 //===----------------------------------------------------------------------===//
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35 // Hexagon V62 Resource Definitions -
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36 //===----------------------------------------------------------------------===//
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