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comparison lib/Target/X86/X86InstrSystem.td @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 3a76565eade5
children
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134:3a76565eade5 147:c2174574ed3a
1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// 1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // This file describes the X86 instructions that are generally used in 9 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are 10 // privileged modes. These are not typically used by the compiler, but are
13 // 12 //
14 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
15 14
16 let SchedRW = [WriteSystem] in { 15 let SchedRW = [WriteSystem] in {
17 let Defs = [RAX, RDX] in 16 let Defs = [RAX, RDX] in
18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>, 17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
19 TB;
20 18
21 let Defs = [RAX, RCX, RDX] in 19 let Defs = [RAX, RCX, RDX] in
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)], 20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23 IIC_RDTSCP>, TB;
24 21
25 // CPU flow control instructions 22 // CPU flow control instructions
26 23
27 let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in { 24 let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
28 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; 25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
29 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB; 26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30 } 27 }
31 28
32 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>; 29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
33 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB; 30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
34 31
35 // Interrupt and SysCall Instructions. 32 // Interrupt and SysCall Instructions.
36 let Uses = [EFLAGS] in 33 let Uses = [EFLAGS] in
37 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>; 34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
38 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", 35
39 [(int_x86_int (i8 3))], IIC_INT3>; 36 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
40 } // SchedRW 37 } // SchedRW
41 38
42 // The long form of "int $3" turns into int3 as a size optimization. 39 // The long form of "int $3" turns into int3 as a size optimization.
43 // FIXME: This doesn't work because InstAlias can't match immediate constants. 40 // FIXME: This doesn't work because InstAlias can't match immediate constants.
44 //def : InstAlias<"int\t$3", (INT3)>; 41 //def : InstAlias<"int\t$3", (INT3)>;
45 42
46 let SchedRW = [WriteSystem] in { 43 let SchedRW = [WriteSystem] in {
47 44
48 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap", 45 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
49 [(int_x86_int imm:$trap)], IIC_INT>; 46 [(int_x86_int imm:$trap)]>;
50 47
51 48
52 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB; 49 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
53 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB; 50 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
54 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB, 51 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
55 Requires<[In64BitMode]>; 52 Requires<[In64BitMode]>;
56 53
57 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [], 54 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
58 IIC_SYS_ENTER_EXIT>, TB; 55
59 56 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
60 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [], 57 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
61 IIC_SYS_ENTER_EXIT>, TB; 58 Requires<[In64BitMode]>;
62 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
63 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
64 } // SchedRW 59 } // SchedRW
65 60
66 def : Pat<(debugtrap), 61 def : Pat<(debugtrap),
67 (INT3)>, Requires<[NotPS4]>; 62 (INT3)>, Requires<[NotPS4]>;
68 def : Pat<(debugtrap), 63 def : Pat<(debugtrap),
71 //===----------------------------------------------------------------------===// 66 //===----------------------------------------------------------------------===//
72 // Input/Output Instructions. 67 // Input/Output Instructions.
73 // 68 //
74 let SchedRW = [WriteSystem] in { 69 let SchedRW = [WriteSystem] in {
75 let Defs = [AL], Uses = [DX] in 70 let Defs = [AL], Uses = [DX] in
76 def IN8rr : I<0xEC, RawFrm, (outs), (ins), 71 def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
77 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
78 let Defs = [AX], Uses = [DX] in 72 let Defs = [AX], Uses = [DX] in
79 def IN16rr : I<0xED, RawFrm, (outs), (ins), 73 def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
80 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16; 74 OpSize16;
81 let Defs = [EAX], Uses = [DX] in 75 let Defs = [EAX], Uses = [DX] in
82 def IN32rr : I<0xED, RawFrm, (outs), (ins), 76 def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
83 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32; 77 OpSize32;
84 78
85 let Defs = [AL] in 79 let Defs = [AL] in
86 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port), 80 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
87 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>; 81 "in{b}\t{$port, %al|al, $port}", []>;
88 let Defs = [AX] in 82 let Defs = [AX] in
89 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 83 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
90 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16; 84 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
91 let Defs = [EAX] in 85 let Defs = [EAX] in
92 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 86 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
93 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32; 87 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
94 88
95 let Uses = [DX, AL] in 89 let Uses = [DX, AL] in
96 def OUT8rr : I<0xEE, RawFrm, (outs), (ins), 90 def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
97 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
98 let Uses = [DX, AX] in 91 let Uses = [DX, AX] in
99 def OUT16rr : I<0xEF, RawFrm, (outs), (ins), 92 def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
100 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16; 93 OpSize16;
101 let Uses = [DX, EAX] in 94 let Uses = [DX, EAX] in
102 def OUT32rr : I<0xEF, RawFrm, (outs), (ins), 95 def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
103 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32; 96 OpSize32;
104 97
105 let Uses = [AL] in 98 let Uses = [AL] in
106 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port), 99 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
107 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>; 100 "out{b}\t{%al, $port|$port, al}", []>;
108 let Uses = [AX] in 101 let Uses = [AX] in
109 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 102 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
110 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16; 103 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
111 let Uses = [EAX] in 104 let Uses = [EAX] in
112 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 105 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
113 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32; 106 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
114 107
115 } // SchedRW 108 } // SchedRW
116 109
117 //===----------------------------------------------------------------------===// 110 //===----------------------------------------------------------------------===//
118 // Moves to and from debug registers 111 // Moves to and from debug registers
119 112
120 let SchedRW = [WriteSystem] in { 113 let SchedRW = [WriteSystem] in {
121 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), 114 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
122 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB, 115 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
123 Requires<[Not64BitMode]>; 116 Requires<[Not64BitMode]>;
124 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), 117 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
125 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB, 118 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
126 Requires<[In64BitMode]>; 119 Requires<[In64BitMode]>;
127 120
128 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 121 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
129 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB, 122 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
130 Requires<[Not64BitMode]>; 123 Requires<[Not64BitMode]>;
131 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 124 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
132 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB, 125 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
133 Requires<[In64BitMode]>; 126 Requires<[In64BitMode]>;
134 } // SchedRW 127 } // SchedRW
135 128
136 //===----------------------------------------------------------------------===// 129 //===----------------------------------------------------------------------===//
137 // Moves to and from control registers 130 // Moves to and from control registers
138 131
139 let SchedRW = [WriteSystem] in { 132 let SchedRW = [WriteSystem] in {
140 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), 133 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
141 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB, 134 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
142 Requires<[Not64BitMode]>; 135 Requires<[Not64BitMode]>;
143 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), 136 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
144 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB, 137 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
145 Requires<[In64BitMode]>; 138 Requires<[In64BitMode]>;
146 139
147 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 140 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
148 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB, 141 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
149 Requires<[Not64BitMode]>; 142 Requires<[Not64BitMode]>;
150 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 143 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
151 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB, 144 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
152 Requires<[In64BitMode]>; 145 Requires<[In64BitMode]>;
153 } // SchedRW 146 } // SchedRW
154 147
155 //===----------------------------------------------------------------------===// 148 //===----------------------------------------------------------------------===//
156 // Segment override instruction prefixes 149 // Segment override instruction prefixes
157 150
158 let SchedRW = [WriteNop] in { 151 let SchedRW = [WriteNop] in {
159 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", [], IIC_NOP>; 152 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
160 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", [], IIC_NOP>; 153 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
161 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", [], IIC_NOP>; 154 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
162 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", [], IIC_NOP>; 155 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
163 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", [], IIC_NOP>; 156 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
164 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", [], IIC_NOP>; 157 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
165 } // SchedRW 158 } // SchedRW
166 159
167 //===----------------------------------------------------------------------===// 160 //===----------------------------------------------------------------------===//
168 // Moves to and from segment registers. 161 // Moves to and from segment registers.
169 // 162 //
170 163
171 let SchedRW = [WriteMove] in { 164 let SchedRW = [WriteMove] in {
172 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), 165 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
173 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16; 166 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
174 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), 167 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
175 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32; 168 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
176 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), 169 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
177 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>; 170 "mov{q}\t{$src, $dst|$dst, $src}", []>;
178 let mayStore = 1 in { 171 let mayStore = 1 in {
179 def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), 172 def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
180 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore; 173 "mov{w}\t{$src, $dst|$dst, $src}", []>;
181 } 174 }
182 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 175 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
183 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16; 176 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
184 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 177 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
185 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32; 178 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
186 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), 179 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
187 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>; 180 "mov{q}\t{$src, $dst|$dst, $src}", []>;
188 let mayLoad = 1 in { 181 let mayLoad = 1 in {
189 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), 182 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
190 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore; 183 "mov{w}\t{$src, $dst|$dst, $src}", []>;
191 } 184 }
192 } // SchedRW 185 } // SchedRW
193 186
194 //===----------------------------------------------------------------------===// 187 //===----------------------------------------------------------------------===//
195 // Segmentation support instructions. 188 // Segmentation support instructions.
196 189
197 let SchedRW = [WriteSystem] in { 190 let SchedRW = [WriteSystem] in {
198 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB; 191 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
199 192
200 let mayLoad = 1 in 193 let mayLoad = 1 in
201 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 194 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
202 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, 195 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
203 OpSize16; 196 OpSize16, NotMemoryFoldable;
204 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 197 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
205 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, 198 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
206 OpSize16; 199 OpSize16, NotMemoryFoldable;
207 200
208 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. 201 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
209 let mayLoad = 1 in 202 let mayLoad = 1 in
210 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 203 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
211 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, 204 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
212 OpSize32; 205 OpSize32, NotMemoryFoldable;
213 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 206 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
214 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, 207 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
215 OpSize32; 208 OpSize32, NotMemoryFoldable;
216 // i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo. 209 // i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo.
217 let mayLoad = 1 in 210 let mayLoad = 1 in
218 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 211 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
219 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB; 212 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
220 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 213 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
221 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB; 214 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
222 215
223 // i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo. 216 // i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo.
224 let mayLoad = 1 in 217 let mayLoad = 1 in
225 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 218 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
226 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, 219 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
227 OpSize16; 220 OpSize16, NotMemoryFoldable;
228 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 221 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
229 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, 222 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
230 OpSize16; 223 OpSize16, NotMemoryFoldable;
231 // i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo. 224 // i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo.
232 let mayLoad = 1 in 225 let mayLoad = 1 in
233 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 226 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
234 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, 227 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
235 OpSize32; 228 OpSize32, NotMemoryFoldable;
236 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 229 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
237 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, 230 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
238 OpSize32; 231 OpSize32, NotMemoryFoldable;
239 let mayLoad = 1 in 232 let mayLoad = 1 in
240 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 233 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
241 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 234 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
242 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 235 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
243 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB; 236 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
244 237
245 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", 238 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
246 [], IIC_INVLPG>, TB;
247 239
248 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 240 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
249 "str{w}\t$dst", [], IIC_STR>, TB, OpSize16; 241 "str{w}\t$dst", []>, TB, OpSize16;
250 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 242 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
251 "str{l}\t$dst", [], IIC_STR>, TB, OpSize32; 243 "str{l}\t$dst", []>, TB, OpSize32;
252 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 244 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
253 "str{q}\t$dst", [], IIC_STR>, TB; 245 "str{q}\t$dst", []>, TB;
254 let mayStore = 1 in 246 let mayStore = 1 in
255 def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), 247 def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
256 "str{w}\t$dst", [], IIC_STR>, TB; 248
257 249 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
258 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), 250 let mayLoad = 1 in
259 "ltr{w}\t$src", [], IIC_LTR>, TB; 251 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
260 let mayLoad = 1 in 252
261 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), 253 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
262 "ltr{w}\t$src", [], IIC_LTR>, TB;
263
264 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
265 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
266 OpSize16, Requires<[Not64BitMode]>; 254 OpSize16, Requires<[Not64BitMode]>;
267 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), 255 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
268 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
269 OpSize32, Requires<[Not64BitMode]>; 256 OpSize32, Requires<[Not64BitMode]>;
270 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), 257 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
271 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
272 OpSize16, Requires<[Not64BitMode]>; 258 OpSize16, Requires<[Not64BitMode]>;
273 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), 259 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
274 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
275 OpSize32, Requires<[Not64BitMode]>; 260 OpSize32, Requires<[Not64BitMode]>;
276 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), 261 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
277 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
278 OpSize16, Requires<[Not64BitMode]>; 262 OpSize16, Requires<[Not64BitMode]>;
279 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), 263 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
280 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
281 OpSize32, Requires<[Not64BitMode]>; 264 OpSize32, Requires<[Not64BitMode]>;
282 def PUSHES16 : I<0x06, RawFrm, (outs), (ins), 265 def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
283 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
284 OpSize16, Requires<[Not64BitMode]>; 266 OpSize16, Requires<[Not64BitMode]>;
285 def PUSHES32 : I<0x06, RawFrm, (outs), (ins), 267 def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
286 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
287 OpSize32, Requires<[Not64BitMode]>; 268 OpSize32, Requires<[Not64BitMode]>;
288 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), 269 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
289 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB; 270 OpSize16, TB;
290 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), 271 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
291 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, 272 OpSize32, Requires<[Not64BitMode]>;
292 OpSize32, Requires<[Not64BitMode]>; 273 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
293 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), 274 OpSize16, TB;
294 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB; 275 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
295 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), 276 OpSize32, Requires<[Not64BitMode]>;
296 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, 277 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
297 OpSize32, Requires<[Not64BitMode]>; 278 OpSize32, Requires<[In64BitMode]>;
298 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), 279 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
299 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, 280 OpSize32, Requires<[In64BitMode]>;
300 OpSize32, Requires<[In64BitMode]>;
301 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
302 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
303 OpSize32, Requires<[In64BitMode]>;
304 281
305 // No "pop cs" instruction. 282 // No "pop cs" instruction.
306 def POPSS16 : I<0x17, RawFrm, (outs), (ins), 283 def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
307 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
308 OpSize16, Requires<[Not64BitMode]>; 284 OpSize16, Requires<[Not64BitMode]>;
309 def POPSS32 : I<0x17, RawFrm, (outs), (ins), 285 def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
310 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
311 OpSize32, Requires<[Not64BitMode]>; 286 OpSize32, Requires<[Not64BitMode]>;
312 287
313 def POPDS16 : I<0x1F, RawFrm, (outs), (ins), 288 def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
314 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
315 OpSize16, Requires<[Not64BitMode]>; 289 OpSize16, Requires<[Not64BitMode]>;
316 def POPDS32 : I<0x1F, RawFrm, (outs), (ins), 290 def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
317 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
318 OpSize32, Requires<[Not64BitMode]>; 291 OpSize32, Requires<[Not64BitMode]>;
319 292
320 def POPES16 : I<0x07, RawFrm, (outs), (ins), 293 def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
321 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
322 OpSize16, Requires<[Not64BitMode]>; 294 OpSize16, Requires<[Not64BitMode]>;
323 def POPES32 : I<0x07, RawFrm, (outs), (ins), 295 def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
324 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
325 OpSize32, Requires<[Not64BitMode]>; 296 OpSize32, Requires<[Not64BitMode]>;
326 297
327 def POPFS16 : I<0xa1, RawFrm, (outs), (ins), 298 def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
328 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB; 299 OpSize16, TB;
329 def POPFS32 : I<0xa1, RawFrm, (outs), (ins), 300 def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
330 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, 301 OpSize32, Requires<[Not64BitMode]>;
331 OpSize32, Requires<[Not64BitMode]>; 302 def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
332 def POPFS64 : I<0xa1, RawFrm, (outs), (ins), 303 OpSize32, Requires<[In64BitMode]>;
333 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, 304
334 OpSize32, Requires<[In64BitMode]>; 305 def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
335 306 OpSize16, TB;
336 def POPGS16 : I<0xa9, RawFrm, (outs), (ins), 307 def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
337 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB; 308 OpSize32, Requires<[Not64BitMode]>;
338 def POPGS32 : I<0xa9, RawFrm, (outs), (ins), 309 def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
339 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, 310 OpSize32, Requires<[In64BitMode]>;
340 OpSize32, Requires<[Not64BitMode]>; 311
341 def POPGS64 : I<0xa9, RawFrm, (outs), (ins), 312 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
342 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, 313 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
343 OpSize32, Requires<[In64BitMode]>;
344
345
346 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
347 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
348 Requires<[Not64BitMode]>; 314 Requires<[Not64BitMode]>;
349 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 315 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
350 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32, 316 "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
351 Requires<[Not64BitMode]>; 317 Requires<[Not64BitMode]>;
352 318
353 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 319 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
354 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16; 320 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
355 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 321 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
356 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32; 322 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
357 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 323 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
358 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 324 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
359 325
360 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 326 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
361 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16, 327 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
362 Requires<[Not64BitMode]>; 328 Requires<[Not64BitMode]>;
363 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 329 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
364 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32, 330 "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
365 Requires<[Not64BitMode]>; 331 Requires<[Not64BitMode]>;
366 332
367 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 333 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
368 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16; 334 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
369 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 335 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
370 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32; 336 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
371 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 337 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
372 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 338 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
373 339
374 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), 340 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
375 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16; 341 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
376 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src), 342 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
377 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32; 343 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
378 344
379 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), 345 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
380 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB; 346 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
381 347
382 348 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
383 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), 349 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
384 "verr\t$seg", [], IIC_VERR>, TB;
385 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
386 "verw\t$seg", [], IIC_VERW_MEM>, TB;
387 let mayLoad = 1 in { 350 let mayLoad = 1 in {
388 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), 351 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
389 "verr\t$seg", [], IIC_VERR>, TB; 352 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
390 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
391 "verw\t$seg", [], IIC_VERW_REG>, TB;
392 } 353 }
393 } // SchedRW 354 } // SchedRW
394 355
395 //===----------------------------------------------------------------------===// 356 //===----------------------------------------------------------------------===//
396 // Descriptor-table support instructions 357 // Descriptor-table support instructions
397 358
398 let SchedRW = [WriteSystem] in { 359 let SchedRW = [WriteSystem] in {
399 def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst), 360 def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
400 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>; 361 "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
401 def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst), 362 def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
402 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>; 363 "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
403 def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst), 364 def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
404 "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>; 365 "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
405 def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst), 366 def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
406 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>; 367 "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
407 def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst), 368 def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
408 "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 369 "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
409 def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst), 370 def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
410 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 371 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
411 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), 372 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
412 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16; 373 "sldt{w}\t$dst", []>, TB, OpSize16;
413 let mayStore = 1 in 374 let mayStore = 1 in
414 def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst), 375 def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
415 "sldt{w}\t$dst", [], IIC_SLDT>, TB; 376 "sldt{w}\t$dst", []>, TB;
416 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), 377 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
417 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB; 378 "sldt{l}\t$dst", []>, OpSize32, TB;
418 379
419 // LLDT is not interpreted specially in 64-bit mode because there is no sign 380 // LLDT is not interpreted specially in 64-bit mode because there is no sign
420 // extension. 381 // extension.
421 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), 382 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
422 "sldt{q}\t$dst", [], IIC_SLDT>, TB, Requires<[In64BitMode]>; 383 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
423 let mayStore = 1 in 384
424 def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst), 385 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
425 "sldt{q}\t$dst", [], IIC_SLDT>, TB, Requires<[In64BitMode]>; 386 "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
426 387 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
427 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), 388 "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
428 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>; 389 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
429 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), 390 "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
430 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>; 391 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
431 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src), 392 "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
432 "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>; 393 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
433 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), 394 "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
434 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>; 395 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
435 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), 396 "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
436 "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
437 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
438 "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
439 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 397 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
440 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB; 398 "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
441 let mayLoad = 1 in 399 let mayLoad = 1 in
442 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), 400 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
443 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB; 401 "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
444 } // SchedRW 402 } // SchedRW
445 403
446 //===----------------------------------------------------------------------===// 404 //===----------------------------------------------------------------------===//
447 // Specialized register support 405 // Specialized register support
448 let SchedRW = [WriteSystem] in { 406 let SchedRW = [WriteSystem] in {
449 let Uses = [EAX, ECX, EDX] in 407 let Uses = [EAX, ECX, EDX] in
450 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB; 408 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
451 let Defs = [EAX, EDX], Uses = [ECX] in 409 let Defs = [EAX, EDX], Uses = [ECX] in
452 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB; 410 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
453 411
454 let Defs = [RAX, RDX], Uses = [ECX] in 412 let Defs = [RAX, RDX], Uses = [ECX] in
455 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>, 413 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
456 TB;
457 414
458 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 415 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
459 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB; 416 "smsw{w}\t$dst", []>, OpSize16, TB;
460 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 417 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
461 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB; 418 "smsw{l}\t$dst", []>, OpSize32, TB;
462 // no m form encodable; use SMSW16m 419 // no m form encodable; use SMSW16m
463 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 420 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
464 "smsw{q}\t$dst", [], IIC_SMSW>, TB; 421 "smsw{q}\t$dst", []>, TB;
465 422
466 // For memory operands, there is only a 16-bit form 423 // For memory operands, there is only a 16-bit form
467 def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst), 424 def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
468 "smsw{w}\t$dst", [], IIC_SMSW>, TB; 425 "smsw{w}\t$dst", []>, TB;
469 426
470 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), 427 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
471 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB; 428 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
472 let mayLoad = 1 in 429 let mayLoad = 1 in
473 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), 430 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
474 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB; 431 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
475 432
476 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in 433 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
477 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB; 434 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
478 } // SchedRW 435 } // SchedRW
479 436
480 //===----------------------------------------------------------------------===// 437 //===----------------------------------------------------------------------===//
481 // Cache instructions 438 // Cache instructions
482 let SchedRW = [WriteSystem] in { 439 let SchedRW = [WriteSystem] in {
483 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB; 440 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
484 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB; 441 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB;
442
443 // wbnoinvd is like wbinvd, except without invalidation
444 // encoding: like wbinvd + an 0xF3 prefix
445 def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
446 [(int_x86_wbnoinvd)]>, XS,
447 Requires<[HasWBNOINVD]>;
485 } // SchedRW 448 } // SchedRW
486 449
487 //===----------------------------------------------------------------------===// 450 //===----------------------------------------------------------------------===//
488 // CET instructions 451 // CET instructions
489 let SchedRW = [WriteSystem], Predicates = [HasSHSTK] in{ 452 // Use with caution, availability is not predicated on features.
453 let SchedRW = [WriteSystem] in {
490 let Uses = [SSP] in { 454 let Uses = [SSP] in {
491 let Defs = [SSP] in { 455 let Defs = [SSP] in {
492 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src", 456 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
493 [(int_x86_incsspd GR32:$src)]>, XS; 457 [(int_x86_incsspd GR32:$src)]>, XS;
494 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src", 458 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
534 498
535 def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), 499 def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
536 "clrssbsy\t$src", 500 "clrssbsy\t$src",
537 [(int_x86_clrssbsy addr:$src)]>, XS; 501 [(int_x86_clrssbsy addr:$src)]>, XS;
538 } // Defs SSP 502 } // Defs SSP
539 } // SchedRW && HasSHSTK 503 } // SchedRW
540 504
541 let SchedRW = [WriteSystem], Predicates = [HasIBT] in { 505 let SchedRW = [WriteSystem] in {
542 def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS; 506 def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
543 def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS; 507 def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
544 } // SchedRW && HasIBT 508 } // SchedRW
545 509
546 //===----------------------------------------------------------------------===// 510 //===----------------------------------------------------------------------===//
547 // XSAVE instructions 511 // XSAVE instructions
548 let SchedRW = [WriteSystem] in { 512 let SchedRW = [WriteSystem] in {
549 let Predicates = [HasXSAVE] in { 513 let Predicates = [HasXSAVE] in {
556 [(int_x86_xsetbv ECX, EDX, EAX)]>, TB; 520 [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
557 521
558 } // HasXSAVE 522 } // HasXSAVE
559 523
560 let Uses = [EDX, EAX] in { 524 let Uses = [EDX, EAX] in {
561 def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst), 525 def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
562 "xsave\t$dst", 526 "xsave\t$dst",
563 [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 527 [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
564 def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst), 528 def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
565 "xsave64\t$dst", 529 "xsave64\t$dst",
566 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 530 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
567 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), 531 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
568 "xrstor\t$dst", 532 "xrstor\t$dst",
569 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 533 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
570 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), 534 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
571 "xrstor64\t$dst", 535 "xrstor64\t$dst",
572 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 536 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
573 def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst), 537 def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
574 "xsaveopt\t$dst", 538 "xsaveopt\t$dst",
575 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>; 539 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
576 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst), 540 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
577 "xsaveopt64\t$dst", 541 "xsaveopt64\t$dst",
578 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>; 542 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
579 def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst), 543 def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
580 "xsavec\t$dst", 544 "xsavec\t$dst",
581 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>; 545 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
582 def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst), 546 def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
583 "xsavec64\t$dst", 547 "xsavec64\t$dst",
584 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>; 548 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
585 def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst), 549 def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
586 "xsaves\t$dst", 550 "xsaves\t$dst",
587 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; 551 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
588 def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst), 552 def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
589 "xsaves64\t$dst", 553 "xsaves64\t$dst",
590 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>; 554 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
591 def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst), 555 def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
592 "xrstors\t$dst", 556 "xrstors\t$dst",
593 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; 557 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
594 def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst), 558 def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
595 "xrstors64\t$dst", 559 "xrstors64\t$dst",
596 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>; 560 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
597 } // Uses 561 } // Uses
598 } // SchedRW 562 } // SchedRW
599 563
621 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB; 585 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
622 } // SchedRW 586 } // SchedRW
623 587
624 //==-----------------------------------------------------------------------===// 588 //==-----------------------------------------------------------------------===//
625 // PKU - enable protection key 589 // PKU - enable protection key
626 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
627 def WRPKRU : PseudoI<(outs), (ins GR32:$src),
628 [(int_x86_wrpkru GR32:$src)]>;
629 def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
630 [(set GR32:$dst, (int_x86_rdpkru))]>;
631 }
632
633 let SchedRW = [WriteSystem] in { 590 let SchedRW = [WriteSystem] in {
634 let Defs = [EAX, EDX], Uses = [ECX] in 591 let Defs = [EAX, EDX], Uses = [ECX] in
635 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", [], IIC_PKU>, TB; 592 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
593 [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, TB;
636 let Uses = [EAX, ECX, EDX] in 594 let Uses = [EAX, ECX, EDX] in
637 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", [], IIC_PKU>, TB; 595 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
596 [(X86wrpkru EAX, EDX, ECX)]>, TB;
638 } // SchedRW 597 } // SchedRW
639 598
640 //===----------------------------------------------------------------------===// 599 //===----------------------------------------------------------------------===//
641 // FS/GS Base Instructions 600 // FS/GS Base Instructions
642 let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in { 601 let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
643 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), 602 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
644 "rdfsbase{l}\t$dst", 603 "rdfsbase{l}\t$dst",
645 [(set GR32:$dst, (int_x86_rdfsbase_32))], 604 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
646 IIC_SEGMENT_BASE_R>, XS;
647 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), 605 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
648 "rdfsbase{q}\t$dst", 606 "rdfsbase{q}\t$dst",
649 [(set GR64:$dst, (int_x86_rdfsbase_64))], 607 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
650 IIC_SEGMENT_BASE_R>, XS;
651 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 608 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
652 "rdgsbase{l}\t$dst", 609 "rdgsbase{l}\t$dst",
653 [(set GR32:$dst, (int_x86_rdgsbase_32))], 610 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
654 IIC_SEGMENT_BASE_R>, XS;
655 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), 611 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
656 "rdgsbase{q}\t$dst", 612 "rdgsbase{q}\t$dst",
657 [(set GR64:$dst, (int_x86_rdgsbase_64))], 613 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
658 IIC_SEGMENT_BASE_R>, XS;
659 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 614 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
660 "wrfsbase{l}\t$src", 615 "wrfsbase{l}\t$src",
661 [(int_x86_wrfsbase_32 GR32:$src)], 616 [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
662 IIC_SEGMENT_BASE_W>, XS;
663 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), 617 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
664 "wrfsbase{q}\t$src", 618 "wrfsbase{q}\t$src",
665 [(int_x86_wrfsbase_64 GR64:$src)], 619 [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
666 IIC_SEGMENT_BASE_W>, XS;
667 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), 620 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
668 "wrgsbase{l}\t$src", 621 "wrgsbase{l}\t$src",
669 [(int_x86_wrgsbase_32 GR32:$src)], IIC_SEGMENT_BASE_W>, XS; 622 [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
670 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), 623 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
671 "wrgsbase{q}\t$src", 624 "wrgsbase{q}\t$src",
672 [(int_x86_wrgsbase_64 GR64:$src)], 625 [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
673 IIC_SEGMENT_BASE_W>, XS;
674 } 626 }
675 627
676 //===----------------------------------------------------------------------===// 628 //===----------------------------------------------------------------------===//
677 // INVPCID Instruction 629 // INVPCID Instruction
678 let SchedRW = [WriteSystem] in { 630 let SchedRW = [WriteSystem] in {
679 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 631 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
680 "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD, 632 "invpcid\t{$src2, $src1|$src1, $src2}",
681 Requires<[Not64BitMode]>; 633 [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
634 Requires<[Not64BitMode, HasINVPCID]>;
682 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 635 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
683 "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD, 636 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
684 Requires<[In64BitMode]>; 637 Requires<[In64BitMode, HasINVPCID]>;
685 } // SchedRW 638 } // SchedRW
639
640 let Predicates = [In64BitMode, HasINVPCID] in {
641 // The instruction can only use a 64 bit register as the register argument
642 // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
643 // corresponding to it.
644 // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
645 // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
646 def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
647 (INVPCID64
648 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
649 addr:$src2)>;
650 }
651
686 652
687 //===----------------------------------------------------------------------===// 653 //===----------------------------------------------------------------------===//
688 // SMAP Instruction 654 // SMAP Instruction
689 let Defs = [EFLAGS], SchedRW = [WriteSystem] in { 655 let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
690 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [], IIC_SMAP>, TB; 656 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
691 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [], IIC_SMAP>, TB; 657 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
692 } 658 }
693 659
694 //===----------------------------------------------------------------------===// 660 //===----------------------------------------------------------------------===//
695 // SMX Instruction 661 // SMX Instruction
696 let SchedRW = [WriteSystem] in { 662 let SchedRW = [WriteSystem] in {
697 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in { 663 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
698 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", [], IIC_SMX>, TB; 664 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
699 } // Uses, Defs 665 } // Uses, Defs
700 } // SchedRW 666 } // SchedRW
701 667
702 //===----------------------------------------------------------------------===// 668 //===----------------------------------------------------------------------===//
669 // TS flag control instruction.
670 let SchedRW = [WriteSystem] in {
671 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
672 }
673
674 //===----------------------------------------------------------------------===//
675 // IF (inside EFLAGS) management instructions.
676 let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
677 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
678 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
679 }
680
681 //===----------------------------------------------------------------------===//
703 // RDPID Instruction 682 // RDPID Instruction
704 let SchedRW = [WriteSystem] in { 683 let SchedRW = [WriteSystem] in {
705 def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 684 def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
706 "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))], IIC_RDPID>, XS, 685 "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
707 Requires<[Not64BitMode, HasRDPID]>; 686 Requires<[Not64BitMode, HasRDPID]>;
708 def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), 687 def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
709 "rdpid\t$dst", [], IIC_RDPID>, XS, 688 Requires<[In64BitMode, HasRDPID]>;
710 Requires<[In64BitMode, HasRDPID]>;
711 } // SchedRW 689 } // SchedRW
712 690
713 let Predicates = [In64BitMode, HasRDPID] in { 691 let Predicates = [In64BitMode, HasRDPID] in {
714 // Due to silly instruction definition, we have to compensate for the 692 // Due to silly instruction definition, we have to compensate for the
715 // instruction outputing a 64-bit register. 693 // instruction outputing a 64-bit register.
717 (EXTRACT_SUBREG (RDPID64), sub_32bit)>; 695 (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
718 } 696 }
719 697
720 698
721 //===----------------------------------------------------------------------===// 699 //===----------------------------------------------------------------------===//
722 // PTWRITE Instruction 700 // PTWRITE Instruction - Write Data to a Processor Trace Packet
723 let SchedRW = [WriteSystem] in { 701 let SchedRW = [WriteSystem] in {
724
725 def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst), 702 def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
726 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS; 703 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
704 Requires<[HasPTWRITE]>;
727 def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst), 705 def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
728 "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS, 706 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
729 Requires<[In64BitMode]>; 707 Requires<[In64BitMode, HasPTWRITE]>;
730 708
731 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst), 709 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
732 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS; 710 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
711 Requires<[HasPTWRITE]>;
733 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst), 712 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
734 "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS, 713 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
735 Requires<[In64BitMode]>; 714 Requires<[In64BitMode, HasPTWRITE]>;
736 } // SchedRW 715 } // SchedRW
716
717 //===----------------------------------------------------------------------===//
718 // Platform Configuration instruction
719
720 // From ISA docs:
721 // "This instruction is used to execute functions for configuring platform
722 // features.
723 // EAX: Leaf function to be invoked.
724 // RBX/RCX/RDX: Leaf-specific purpose."
725 // "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
726 // AF, OF, and SF are cleared. In case of failure, the failure reason is
727 // indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
728 // Thus all these mentioned registers are considered clobbered.
729
730 let SchedRW = [WriteSystem] in {
731 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
732 def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
733 Requires<[HasPCONFIG]>;
734 } // SchedRW