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1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
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2 //
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147
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file describes the X86 instructions that are generally used in
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10 // privileged modes. These are not typically used by the compiler, but are
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11 // supported for the assembler and disassembler.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 let SchedRW = [WriteSystem] in {
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16 let Defs = [RAX, RDX] in
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17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
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18
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19 let Defs = [RAX, RCX, RDX] in
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20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
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21
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22 // CPU flow control instructions
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23
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24 let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
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25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
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26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
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27 }
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28
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29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
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30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
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31
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32 // Interrupt and SysCall Instructions.
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33 let Uses = [EFLAGS] in
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34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
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35
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36 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
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37 } // SchedRW
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38
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39 // The long form of "int $3" turns into int3 as a size optimization.
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40 // FIXME: This doesn't work because InstAlias can't match immediate constants.
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41 //def : InstAlias<"int\t$3", (INT3)>;
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42
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43 let SchedRW = [WriteSystem] in {
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44
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45 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
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46 [(int_x86_int imm:$trap)]>;
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47
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48
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49 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
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50 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
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51 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
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52 Requires<[In64BitMode]>;
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53
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54 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
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55
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56 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
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57 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
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58 Requires<[In64BitMode]>;
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59 } // SchedRW
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60
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83
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61 def : Pat<(debugtrap),
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62 (INT3)>, Requires<[NotPS4]>;
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63 def : Pat<(debugtrap),
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64 (INT (i8 0x41))>, Requires<[IsPS4]>;
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65
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66 //===----------------------------------------------------------------------===//
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67 // Input/Output Instructions.
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68 //
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69 let SchedRW = [WriteSystem] in {
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70 let Defs = [AL], Uses = [DX] in
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71 def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
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72 let Defs = [AX], Uses = [DX] in
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147
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73 def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
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74 OpSize16;
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75 let Defs = [EAX], Uses = [DX] in
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147
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76 def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
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77 OpSize32;
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78
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79 let Defs = [AL] in
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95
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80 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
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81 "in{b}\t{$port, %al|al, $port}", []>;
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82 let Defs = [AX] in
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83 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
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84 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
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85 let Defs = [EAX] in
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95
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86 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
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87 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
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88
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89 let Uses = [DX, AL] in
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90 def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
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91 let Uses = [DX, AX] in
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92 def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
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93 OpSize16;
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94 let Uses = [DX, EAX] in
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95 def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
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96 OpSize32;
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97
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98 let Uses = [AL] in
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95
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99 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
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100 "out{b}\t{%al, $port|$port, al}", []>;
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101 let Uses = [AX] in
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95
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102 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
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103 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
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104 let Uses = [EAX] in
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95
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105 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
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147
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106 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
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107
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108 } // SchedRW
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109
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110 //===----------------------------------------------------------------------===//
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111 // Moves to and from debug registers
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112
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113 let SchedRW = [WriteSystem] in {
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114 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
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147
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115 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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116 Requires<[Not64BitMode]>;
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117 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
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147
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118 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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119 Requires<[In64BitMode]>;
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120
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121 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
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147
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122 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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123 Requires<[Not64BitMode]>;
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124 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
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147
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125 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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126 Requires<[In64BitMode]>;
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127 } // SchedRW
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128
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129 //===----------------------------------------------------------------------===//
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130 // Moves to and from control registers
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131
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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132 let SchedRW = [WriteSystem] in {
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133 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
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147
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134 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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135 Requires<[Not64BitMode]>;
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136 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
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147
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137 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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138 Requires<[In64BitMode]>;
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139
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140 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
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147
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141 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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142 Requires<[Not64BitMode]>;
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143 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
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147
|
144 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
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77
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145 Requires<[In64BitMode]>;
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146 } // SchedRW
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147
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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148 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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149 // Segment override instruction prefixes
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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150
|
|
134
|
151 let SchedRW = [WriteNop] in {
|
|
147
|
152 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
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153 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
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154 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
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155 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
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156 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
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157 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
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134
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158 } // SchedRW
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159
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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160 //===----------------------------------------------------------------------===//
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161 // Moves to and from segment registers.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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162 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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163
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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164 let SchedRW = [WriteMove] in {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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165 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
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|
147
|
166 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
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167 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
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147
|
168 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
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169 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
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147
|
170 "mov{q}\t{$src, $dst|$dst, $src}", []>;
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|
121
|
171 let mayStore = 1 in {
|
|
120
|
172 def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
|
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147
|
173 "mov{w}\t{$src, $dst|$dst, $src}", []>;
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|
121
|
174 }
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175 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
|
|
147
|
176 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
|
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177 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
|
|
147
|
178 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
|
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179 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
|
|
147
|
180 "mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
121
|
181 let mayLoad = 1 in {
|
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182 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
|
|
147
|
183 "mov{w}\t{$src, $dst|$dst, $src}", []>;
|
|
121
|
184 }
|
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185 } // SchedRW
|
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186
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187 //===----------------------------------------------------------------------===//
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188 // Segmentation support instructions.
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189
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190 let SchedRW = [WriteSystem] in {
|
|
147
|
191 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
|
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192
|
|
121
|
193 let mayLoad = 1 in
|
|
83
|
194 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|
147
|
195 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
196 OpSize16, NotMemoryFoldable;
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197 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|
147
|
198 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
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|
|
199 OpSize16, NotMemoryFoldable;
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200
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201 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
|
|
121
|
202 let mayLoad = 1 in
|
|
83
|
203 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
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147
|
204 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
205 OpSize32, NotMemoryFoldable;
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206 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
147
|
207 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
208 OpSize32, NotMemoryFoldable;
|
|
134
|
209 // i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo.
|
|
121
|
210 let mayLoad = 1 in
|
|
83
|
211 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
|
147
|
212 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
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213 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
|
|
147
|
214 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
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215
|
|
134
|
216 // i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo.
|
|
121
|
217 let mayLoad = 1 in
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218 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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147
|
219 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
220 OpSize16, NotMemoryFoldable;
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|
221 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|
147
|
222 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
223 OpSize16, NotMemoryFoldable;
|
|
134
|
224 // i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo.
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|
121
|
225 let mayLoad = 1 in
|
|
134
|
226 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
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147
|
227 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
228 OpSize32, NotMemoryFoldable;
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229 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|
147
|
230 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
|
|
|
231 OpSize32, NotMemoryFoldable;
|
|
121
|
232 let mayLoad = 1 in
|
|
134
|
233 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
|
147
|
234 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
|
|
134
|
235 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
|
|
147
|
236 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
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237
|
|
147
|
238 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
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239
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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240 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
|
|
147
|
241 "str{w}\t$dst", []>, TB, OpSize16;
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242 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
|
|
147
|
243 "str{l}\t$dst", []>, TB, OpSize32;
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244 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
|
|
147
|
245 "str{q}\t$dst", []>, TB;
|
|
121
|
246 let mayStore = 1 in
|
|
147
|
247 def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
|
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248
|
|
147
|
249 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
|
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121
|
250 let mayLoad = 1 in
|
|
147
|
251 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
|
|
83
|
252
|
|
147
|
253 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
|
|
77
|
254 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
255 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
|
|
77
|
256 OpSize32, Requires<[Not64BitMode]>;
|
|
147
|
257 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
|
|
77
|
258 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
259 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
|
|
77
|
260 OpSize32, Requires<[Not64BitMode]>;
|
|
147
|
261 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
|
|
77
|
262 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
263 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
|
|
77
|
264 OpSize32, Requires<[Not64BitMode]>;
|
|
147
|
265 def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
|
|
77
|
266 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
267 def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
|
|
77
|
268 OpSize32, Requires<[Not64BitMode]>;
|
|
147
|
269 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
|
|
|
270 OpSize16, TB;
|
|
|
271 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
|
|
|
272 OpSize32, Requires<[Not64BitMode]>;
|
|
|
273 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
|
|
|
274 OpSize16, TB;
|
|
|
275 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
|
|
|
276 OpSize32, Requires<[Not64BitMode]>;
|
|
|
277 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
|
|
|
278 OpSize32, Requires<[In64BitMode]>;
|
|
|
279 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
|
|
|
280 OpSize32, Requires<[In64BitMode]>;
|
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|
281
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
282 // No "pop cs" instruction.
|
|
147
|
283 def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
|
|
77
|
284 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
285 def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
|
|
77
|
286 OpSize32, Requires<[Not64BitMode]>;
|
|
|
287
|
|
147
|
288 def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
|
|
77
|
289 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
290 def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
|
|
77
|
291 OpSize32, Requires<[Not64BitMode]>;
|
|
|
292
|
|
147
|
293 def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
|
|
77
|
294 OpSize16, Requires<[Not64BitMode]>;
|
|
147
|
295 def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
|
|
77
|
296 OpSize32, Requires<[Not64BitMode]>;
|
|
|
297
|
|
147
|
298 def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
|
|
|
299 OpSize16, TB;
|
|
|
300 def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
|
|
|
301 OpSize32, Requires<[Not64BitMode]>;
|
|
|
302 def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
|
|
|
303 OpSize32, Requires<[In64BitMode]>;
|
|
77
|
304
|
|
147
|
305 def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
|
|
|
306 OpSize16, TB;
|
|
|
307 def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
|
|
|
308 OpSize32, Requires<[Not64BitMode]>;
|
|
|
309 def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
|
|
|
310 OpSize32, Requires<[In64BitMode]>;
|
|
77
|
311
|
|
147
|
312 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
|
|
|
313 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
|
|
100
|
314 Requires<[Not64BitMode]>;
|
|
147
|
315 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
|
|
|
316 "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
|
|
100
|
317 Requires<[Not64BitMode]>;
|
|
83
|
318
|
|
147
|
319 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
|
|
|
320 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
|
|
|
321 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
|
|
|
322 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
|
|
|
323 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
|
|
|
324 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
83
|
325
|
|
147
|
326 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
|
|
|
327 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
|
|
100
|
328 Requires<[Not64BitMode]>;
|
|
147
|
329 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
|
|
|
330 "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
|
|
100
|
331 Requires<[Not64BitMode]>;
|
|
83
|
332
|
|
147
|
333 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
|
|
|
334 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
|
|
|
335 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
|
|
|
336 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
|
|
|
337 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
|
|
|
338 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
83
|
339
|
|
147
|
340 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
|
|
|
341 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
|
|
|
342 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
|
|
|
343 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
344
|
|
147
|
345 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
|
|
|
346 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
347
|
|
|
348 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
|
|
|
349 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
|
|
121
|
350 let mayLoad = 1 in {
|
|
147
|
351 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
|
|
|
352 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
|
|
121
|
353 }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
354 } // SchedRW
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
355
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
356 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
357 // Descriptor-table support instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
358
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
359 let SchedRW = [WriteSystem] in {
|
|
147
|
360 def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
|
|
|
361 "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
|
|
|
362 def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
|
|
|
363 "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
|
|
|
364 def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
|
|
|
365 "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
|
|
|
366 def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
|
|
|
367 "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
|
|
|
368 def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
|
|
|
369 "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
|
|
|
370 def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
|
|
|
371 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
372 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
|
147
|
373 "sldt{w}\t$dst", []>, TB, OpSize16;
|
|
121
|
374 let mayStore = 1 in
|
|
120
|
375 def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
|
|
147
|
376 "sldt{w}\t$dst", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
377 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
|
|
147
|
378 "sldt{l}\t$dst", []>, OpSize32, TB;
|
|
83
|
379
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
380 // LLDT is not interpreted specially in 64-bit mode because there is no sign
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
381 // extension.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
382 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
|
|
147
|
383 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
384
|
|
147
|
385 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
|
|
|
386 "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
|
|
|
387 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
|
|
|
388 "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
|
|
|
389 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
|
|
|
390 "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
|
|
|
391 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
|
|
|
392 "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
|
|
|
393 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
|
|
|
394 "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
|
|
|
395 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
|
|
|
396 "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
397 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
|
147
|
398 "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
|
|
121
|
399 let mayLoad = 1 in
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
400 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
|
|
147
|
401 "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
402 } // SchedRW
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
403
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
404 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 // Specialized register support
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 let SchedRW = [WriteSystem] in {
|
|
83
|
407 let Uses = [EAX, ECX, EDX] in
|
|
147
|
408 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
|
|
83
|
409 let Defs = [EAX, EDX], Uses = [ECX] in
|
|
147
|
410 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
|
|
77
|
411
|
|
|
412 let Defs = [RAX, RDX], Uses = [ECX] in
|
|
147
|
413 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
414
|
|
83
|
415 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
|
147
|
416 "smsw{w}\t$dst", []>, OpSize16, TB;
|
|
83
|
417 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
|
147
|
418 "smsw{l}\t$dst", []>, OpSize32, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
419 // no m form encodable; use SMSW16m
|
|
83
|
420 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
|
|
147
|
421 "smsw{q}\t$dst", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
422
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
423 // For memory operands, there is only a 16-bit form
|
|
120
|
424 def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
|
|
147
|
425 "smsw{w}\t$dst", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
426
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
427 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
|
147
|
428 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
|
|
121
|
429 let mayLoad = 1 in
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
|
|
147
|
431 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
|
|
77
|
432
|
|
|
433 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
|
|
147
|
434 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 } // SchedRW
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438 // Cache instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
439 let SchedRW = [WriteSystem] in {
|
|
147
|
440 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
|
|
|
441 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB;
|
|
|
442
|
|
|
443 // wbnoinvd is like wbinvd, except without invalidation
|
|
|
444 // encoding: like wbinvd + an 0xF3 prefix
|
|
|
445 def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
|
|
|
446 [(int_x86_wbnoinvd)]>, XS,
|
|
|
447 Requires<[HasWBNOINVD]>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
448 } // SchedRW
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450 //===----------------------------------------------------------------------===//
|
|
134
|
451 // CET instructions
|
|
147
|
452 // Use with caution, availability is not predicated on features.
|
|
|
453 let SchedRW = [WriteSystem] in {
|
|
134
|
454 let Uses = [SSP] in {
|
|
|
455 let Defs = [SSP] in {
|
|
|
456 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
|
|
|
457 [(int_x86_incsspd GR32:$src)]>, XS;
|
|
|
458 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
|
|
|
459 [(int_x86_incsspq GR64:$src)]>, XS;
|
|
|
460 } // Defs SSP
|
|
|
461
|
|
|
462 let Constraints = "$src = $dst" in {
|
|
|
463 def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
|
|
|
464 "rdsspd\t$dst",
|
|
|
465 [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
|
|
|
466 def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
|
|
|
467 "rdsspq\t$dst",
|
|
|
468 [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
|
|
|
469 }
|
|
|
470
|
|
|
471 let Defs = [SSP] in {
|
|
|
472 def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
|
|
|
473 [(int_x86_saveprevssp)]>, XS;
|
|
|
474 def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
|
|
|
475 "rstorssp\t$src",
|
|
|
476 [(int_x86_rstorssp addr:$src)]>, XS;
|
|
|
477 } // Defs SSP
|
|
|
478 } // Uses SSP
|
|
|
479
|
|
|
480 def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|
|
481 "wrssd\t{$src, $dst|$dst, $src}",
|
|
|
482 [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
|
|
|
483 def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
|
484 "wrssq\t{$src, $dst|$dst, $src}",
|
|
|
485 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
|
|
|
486 def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|
|
487 "wrussd\t{$src, $dst|$dst, $src}",
|
|
|
488 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
|
|
|
489 def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
|
490 "wrussq\t{$src, $dst|$dst, $src}",
|
|
|
491 [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
|
|
|
492
|
|
|
493 let Defs = [SSP] in {
|
|
|
494 let Uses = [SSP] in {
|
|
|
495 def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
|
|
|
496 [(int_x86_setssbsy)]>, XS;
|
|
|
497 } // Uses SSP
|
|
|
498
|
|
|
499 def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
|
|
|
500 "clrssbsy\t$src",
|
|
|
501 [(int_x86_clrssbsy addr:$src)]>, XS;
|
|
|
502 } // Defs SSP
|
|
147
|
503 } // SchedRW
|
|
134
|
504
|
|
147
|
505 let SchedRW = [WriteSystem] in {
|
|
134
|
506 def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
|
|
|
507 def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
|
|
147
|
508 } // SchedRW
|
|
134
|
509
|
|
|
510 //===----------------------------------------------------------------------===//
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
511 // XSAVE instructions
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
512 let SchedRW = [WriteSystem] in {
|
|
95
|
513 let Predicates = [HasXSAVE] in {
|
|
77
|
514 let Defs = [EDX, EAX], Uses = [ECX] in
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
516
|
|
77
|
517 let Uses = [EDX, EAX, ECX] in
|
|
134
|
518 def XSETBV : I<0x01, MRM_D1, (outs), (ins),
|
|
|
519 "xsetbv",
|
|
120
|
520 [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
|
|
|
521
|
|
|
522 } // HasXSAVE
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
523
|
|
95
|
524 let Uses = [EDX, EAX] in {
|
|
147
|
525 def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
|
|
134
|
526 "xsave\t$dst",
|
|
|
527 [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
|
|
147
|
528 def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
|
|
134
|
529 "xsave64\t$dst",
|
|
|
530 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
|
|
147
|
531 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
|
|
134
|
532 "xrstor\t$dst",
|
|
|
533 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
|
|
147
|
534 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
|
|
134
|
535 "xrstor64\t$dst",
|
|
|
536 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
|
|
147
|
537 def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
|
|
134
|
538 "xsaveopt\t$dst",
|
|
|
539 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
|
|
147
|
540 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
|
|
134
|
541 "xsaveopt64\t$dst",
|
|
|
542 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
|
|
147
|
543 def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
|
|
134
|
544 "xsavec\t$dst",
|
|
|
545 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
|
|
147
|
546 def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
|
|
134
|
547 "xsavec64\t$dst",
|
|
|
548 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
|
|
147
|
549 def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
|
|
134
|
550 "xsaves\t$dst",
|
|
|
551 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
|
|
147
|
552 def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
|
|
134
|
553 "xsaves64\t$dst",
|
|
|
554 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
|
|
147
|
555 def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
|
|
134
|
556 "xrstors\t$dst",
|
|
|
557 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
|
|
147
|
558 def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
|
|
134
|
559 "xrstors64\t$dst",
|
|
|
560 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
|
|
95
|
561 } // Uses
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
562 } // SchedRW
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
563
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
564 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
565 // VIA PadLock crypto instructions
|
|
134
|
566 let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
|
|
77
|
567 def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
568
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
569 def : InstAlias<"xstorerng", (XSTORE)>;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
570
|
|
134
|
571 let SchedRW = [WriteSystem] in {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
572 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
|
|
77
|
573 def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
|
|
|
574 def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
|
|
|
575 def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
|
|
|
576 def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
|
|
|
577 def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
578 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
579
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
580 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
|
|
77
|
581 def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
|
|
|
582 def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
583 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
584 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
|
|
77
|
585 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
|
|
134
|
586 } // SchedRW
|
|
|
587
|
|
100
|
588 //==-----------------------------------------------------------------------===//
|
|
|
589 // PKU - enable protection key
|
|
134
|
590 let SchedRW = [WriteSystem] in {
|
|
120
|
591 let Defs = [EAX, EDX], Uses = [ECX] in
|
|
147
|
592 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
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|
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593 [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, TB;
|
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100
|
594 let Uses = [EAX, ECX, EDX] in
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147
|
595 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
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596 [(X86wrpkru EAX, EDX, ECX)]>, TB;
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134
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597 } // SchedRW
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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598
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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599 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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600 // FS/GS Base Instructions
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134
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601 let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
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0
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602 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
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603 "rdfsbase{l}\t$dst",
|
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147
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604 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
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0
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605 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
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606 "rdfsbase{q}\t$dst",
|
|
147
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607 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
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608 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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609 "rdgsbase{l}\t$dst",
|
|
147
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610 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
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611 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
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612 "rdgsbase{q}\t$dst",
|
|
147
|
613 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
|
0
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614 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
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615 "wrfsbase{l}\t$src",
|
|
147
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616 [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
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0
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617 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
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618 "wrfsbase{q}\t$src",
|
|
147
|
619 [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
|
0
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620 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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621 "wrgsbase{l}\t$src",
|
|
147
|
622 [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
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0
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parents:
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|
623 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
624 "wrgsbase{q}\t$src",
|
|
147
|
625 [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
|
0
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626 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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627
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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628 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
629 // INVPCID Instruction
|
|
134
|
630 let SchedRW = [WriteSystem] in {
|
0
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parents:
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|
631 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
|
|
147
|
632 "invpcid\t{$src2, $src1|$src1, $src2}",
|
|
|
633 [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
|
|
|
634 Requires<[Not64BitMode, HasINVPCID]>;
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
635 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
|
|
147
|
636 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
|
|
|
637 Requires<[In64BitMode, HasINVPCID]>;
|
|
134
|
638 } // SchedRW
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
639
|
|
147
|
640 let Predicates = [In64BitMode, HasINVPCID] in {
|
|
|
641 // The instruction can only use a 64 bit register as the register argument
|
|
|
642 // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
|
|
|
643 // corresponding to it.
|
|
|
644 // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
|
|
|
645 // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
|
|
|
646 def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
|
|
|
647 (INVPCID64
|
|
|
648 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
|
|
|
649 addr:$src2)>;
|
|
|
650 }
|
|
|
651
|
|
|
652
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
653 //===----------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
654 // SMAP Instruction
|
|
134
|
655 let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
|
|
147
|
656 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
|
|
|
657 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
658 }
|
|
83
|
659
|
|
|
660 //===----------------------------------------------------------------------===//
|
|
|
661 // SMX Instruction
|
|
134
|
662 let SchedRW = [WriteSystem] in {
|
|
83
|
663 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
|
|
147
|
664 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
|
|
134
|
665 } // Uses, Defs
|
|
|
666 } // SchedRW
|
|
121
|
667
|
|
|
668 //===----------------------------------------------------------------------===//
|
|
147
|
669 // TS flag control instruction.
|
|
|
670 let SchedRW = [WriteSystem] in {
|
|
|
671 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
|
|
|
672 }
|
|
|
673
|
|
|
674 //===----------------------------------------------------------------------===//
|
|
|
675 // IF (inside EFLAGS) management instructions.
|
|
|
676 let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
|
|
|
677 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
|
|
|
678 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
|
|
|
679 }
|
|
|
680
|
|
|
681 //===----------------------------------------------------------------------===//
|
|
121
|
682 // RDPID Instruction
|
|
134
|
683 let SchedRW = [WriteSystem] in {
|
|
|
684 def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
|
|
147
|
685 "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
|
|
|
686 Requires<[Not64BitMode, HasRDPID]>;
|
|
|
687 def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
|
|
|
688 Requires<[In64BitMode, HasRDPID]>;
|
|
134
|
689 } // SchedRW
|
|
|
690
|
|
|
691 let Predicates = [In64BitMode, HasRDPID] in {
|
|
|
692 // Due to silly instruction definition, we have to compensate for the
|
|
|
693 // instruction outputing a 64-bit register.
|
|
|
694 def : Pat<(int_x86_rdpid),
|
|
|
695 (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
|
|
|
696 }
|
|
|
697
|
|
121
|
698
|
|
|
699 //===----------------------------------------------------------------------===//
|
|
147
|
700 // PTWRITE Instruction - Write Data to a Processor Trace Packet
|
|
134
|
701 let SchedRW = [WriteSystem] in {
|
|
121
|
702 def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
|
|
147
|
703 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
|
|
|
704 Requires<[HasPTWRITE]>;
|
|
121
|
705 def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
|
|
147
|
706 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
|
|
|
707 Requires<[In64BitMode, HasPTWRITE]>;
|
|
121
|
708
|
|
|
709 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
|
|
147
|
710 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
|
|
|
711 Requires<[HasPTWRITE]>;
|
|
121
|
712 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
|
|
147
|
713 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
|
|
|
714 Requires<[In64BitMode, HasPTWRITE]>;
|
|
134
|
715 } // SchedRW
|
|
147
|
716
|
|
|
717 //===----------------------------------------------------------------------===//
|
|
|
718 // Platform Configuration instruction
|
|
|
719
|
|
|
720 // From ISA docs:
|
|
|
721 // "This instruction is used to execute functions for configuring platform
|
|
|
722 // features.
|
|
|
723 // EAX: Leaf function to be invoked.
|
|
|
724 // RBX/RCX/RDX: Leaf-specific purpose."
|
|
|
725 // "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
|
|
|
726 // AF, OF, and SF are cleared. In case of failure, the failure reason is
|
|
|
727 // indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
|
|
|
728 // Thus all these mentioned registers are considered clobbered.
|
|
|
729
|
|
|
730 let SchedRW = [WriteSystem] in {
|
|
|
731 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
|
|
|
732 def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
|
|
|
733 Requires<[HasPCONFIG]>;
|
|
|
734 } // SchedRW
|
