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comparison test/Transforms/InstCombine/select-bitext.ll @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 803732b1fca8
children
comparison
equal deleted inserted replaced
134:3a76565eade5 147:c2174574ed3a
3 3
4 ; Widen a select of constants to eliminate an extend. 4 ; Widen a select of constants to eliminate an extend.
5 5
6 define i16 @sel_sext_constants(i1 %cmp) { 6 define i16 @sel_sext_constants(i1 %cmp) {
7 ; CHECK-LABEL: @sel_sext_constants( 7 ; CHECK-LABEL: @sel_sext_constants(
8 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i16 -1, i16 42 8 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i16 -1, i16 42
9 ; CHECK-NEXT: ret i16 [[EXT]] 9 ; CHECK-NEXT: ret i16 [[EXT]]
10 ; 10 ;
11 %sel = select i1 %cmp, i8 255, i8 42 11 %sel = select i1 %cmp, i8 255, i8 42
12 %ext = sext i8 %sel to i16 12 %ext = sext i8 %sel to i16
13 ret i16 %ext 13 ret i16 %ext
14 } 14 }
15 15
16 define i16 @sel_zext_constants(i1 %cmp) { 16 define i16 @sel_zext_constants(i1 %cmp) {
17 ; CHECK-LABEL: @sel_zext_constants( 17 ; CHECK-LABEL: @sel_zext_constants(
18 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i16 255, i16 42 18 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i16 255, i16 42
19 ; CHECK-NEXT: ret i16 [[EXT]] 19 ; CHECK-NEXT: ret i16 [[EXT]]
20 ; 20 ;
21 %sel = select i1 %cmp, i8 255, i8 42 21 %sel = select i1 %cmp, i8 255, i8 42
22 %ext = zext i8 %sel to i16 22 %ext = zext i8 %sel to i16
23 ret i16 %ext 23 ret i16 %ext
24 } 24 }
25 25
26 define double @sel_fpext_constants(i1 %cmp) { 26 define double @sel_fpext_constants(i1 %cmp) {
27 ; CHECK-LABEL: @sel_fpext_constants( 27 ; CHECK-LABEL: @sel_fpext_constants(
28 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, double -2.550000e+02, double 4.200000e+01 28 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], double -2.550000e+02, double 4.200000e+01
29 ; CHECK-NEXT: ret double [[EXT]] 29 ; CHECK-NEXT: ret double [[EXT]]
30 ; 30 ;
31 %sel = select i1 %cmp, float -255.0, float 42.0 31 %sel = select i1 %cmp, float -255.0, float 42.0
32 %ext = fpext float %sel to double 32 %ext = fpext float %sel to double
33 ret double %ext 33 ret double %ext
35 35
36 ; FIXME: We should not grow the size of the select in the next 4 cases. 36 ; FIXME: We should not grow the size of the select in the next 4 cases.
37 37
38 define i64 @sel_sext(i32 %a, i1 %cmp) { 38 define i64 @sel_sext(i32 %a, i1 %cmp) {
39 ; CHECK-LABEL: @sel_sext( 39 ; CHECK-LABEL: @sel_sext(
40 ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 %a to i64 40 ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[A:%.*]] to i64
41 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42 41 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
42 ; CHECK-NEXT: ret i64 [[EXT]] 42 ; CHECK-NEXT: ret i64 [[EXT]]
43 ; 43 ;
44 %sel = select i1 %cmp, i32 %a, i32 42 44 %sel = select i1 %cmp, i32 %a, i32 42
45 %ext = sext i32 %sel to i64 45 %ext = sext i32 %sel to i64
46 ret i64 %ext 46 ret i64 %ext
47 } 47 }
48 48
49 define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) { 49 define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) {
50 ; CHECK-LABEL: @sel_sext_vec( 50 ; CHECK-LABEL: @sel_sext_vec(
51 ; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> %a to <4 x i64> 51 ; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> [[A:%.*]] to <4 x i64>
52 ; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42> 52 ; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
53 ; CHECK-NEXT: ret <4 x i64> [[EXT]] 53 ; CHECK-NEXT: ret <4 x i64> [[EXT]]
54 ; 54 ;
55 %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42> 55 %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
56 %ext = sext <4 x i32> %sel to <4 x i64> 56 %ext = sext <4 x i32> %sel to <4 x i64>
57 ret <4 x i64> %ext 57 ret <4 x i64> %ext
58 } 58 }
59 59
60 define i64 @sel_zext(i32 %a, i1 %cmp) { 60 define i64 @sel_zext(i32 %a, i1 %cmp) {
61 ; CHECK-LABEL: @sel_zext( 61 ; CHECK-LABEL: @sel_zext(
62 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 %a to i64 62 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
63 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42 63 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
64 ; CHECK-NEXT: ret i64 [[EXT]] 64 ; CHECK-NEXT: ret i64 [[EXT]]
65 ; 65 ;
66 %sel = select i1 %cmp, i32 %a, i32 42 66 %sel = select i1 %cmp, i32 %a, i32 42
67 %ext = zext i32 %sel to i64 67 %ext = zext i32 %sel to i64
68 ret i64 %ext 68 ret i64 %ext
69 } 69 }
70 70
71 define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) { 71 define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {
72 ; CHECK-LABEL: @sel_zext_vec( 72 ; CHECK-LABEL: @sel_zext_vec(
73 ; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> %a to <4 x i64> 73 ; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> [[A:%.*]] to <4 x i64>
74 ; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42> 74 ; CHECK-NEXT: [[EXT:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
75 ; CHECK-NEXT: ret <4 x i64> [[EXT]] 75 ; CHECK-NEXT: ret <4 x i64> [[EXT]]
76 ; 76 ;
77 %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42> 77 %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
78 %ext = zext <4 x i32> %sel to <4 x i64> 78 %ext = zext <4 x i32> %sel to <4 x i64>
79 ret <4 x i64> %ext 79 ret <4 x i64> %ext
83 ; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only 83 ; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only
84 ; way to justify widening the select. 84 ; way to justify widening the select.
85 85
86 define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) { 86 define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) {
87 ; CHECK-LABEL: @trunc_sel_larger_sext( 87 ; CHECK-LABEL: @trunc_sel_larger_sext(
88 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 %a to i16 88 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[A:%.*]] to i16
89 ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64 89 ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64
90 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42 90 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
91 ; CHECK-NEXT: ret i64 [[EXT]] 91 ; CHECK-NEXT: ret i64 [[EXT]]
92 ; 92 ;
93 %trunc = trunc i32 %a to i16 93 %trunc = trunc i32 %a to i16
94 %sel = select i1 %cmp, i16 %trunc, i16 42 94 %sel = select i1 %cmp, i16 %trunc, i16 42
95 %ext = sext i16 %sel to i64 95 %ext = sext i16 %sel to i64
96 ret i64 %ext 96 ret i64 %ext
97 } 97 }
98 98
99 define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) { 99 define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
100 ; CHECK-LABEL: @trunc_sel_larger_sext_vec( 100 ; CHECK-LABEL: @trunc_sel_larger_sext_vec(
101 ; CHECK-NEXT: [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64> 101 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i32> [[A:%.*]] to <2 x i16>
102 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48> 102 ; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TRUNC]] to <2 x i64>
103 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i64> [[SEXT]], <i64 48, i64 48> 103 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
104 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
105 ; CHECK-NEXT: ret <2 x i64> [[EXT]] 104 ; CHECK-NEXT: ret <2 x i64> [[EXT]]
106 ; 105 ;
107 %trunc = trunc <2 x i32> %a to <2 x i16> 106 %trunc = trunc <2 x i32> %a to <2 x i16>
108 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43> 107 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
109 %ext = sext <2 x i16> %sel to <2 x i64> 108 %ext = sext <2 x i16> %sel to <2 x i64>
110 ret <2 x i64> %ext 109 ret <2 x i64> %ext
111 } 110 }
112 111
113 define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) { 112 define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) {
114 ; CHECK-LABEL: @trunc_sel_smaller_sext( 113 ; CHECK-LABEL: @trunc_sel_smaller_sext(
115 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 %a to i16 114 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[A:%.*]] to i16
116 ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32 115 ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32
117 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42 116 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP1]], i32 42
118 ; CHECK-NEXT: ret i32 [[EXT]] 117 ; CHECK-NEXT: ret i32 [[EXT]]
119 ; 118 ;
120 %trunc = trunc i64 %a to i16 119 %trunc = trunc i64 %a to i16
121 %sel = select i1 %cmp, i16 %trunc, i16 42 120 %sel = select i1 %cmp, i16 %trunc, i16 42
122 %ext = sext i16 %sel to i32 121 %ext = sext i16 %sel to i32
123 ret i32 %ext 122 ret i32 %ext
124 } 123 }
125 124
126 define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) { 125 define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) {
127 ; CHECK-LABEL: @trunc_sel_smaller_sext_vec( 126 ; CHECK-LABEL: @trunc_sel_smaller_sext_vec(
128 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32> 127 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i16>
129 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16> 128 ; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TRUNC]] to <2 x i32>
130 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16> 129 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
131 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
132 ; CHECK-NEXT: ret <2 x i32> [[EXT]] 130 ; CHECK-NEXT: ret <2 x i32> [[EXT]]
133 ; 131 ;
134 %trunc = trunc <2 x i64> %a to <2 x i16> 132 %trunc = trunc <2 x i64> %a to <2 x i16>
135 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43> 133 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
136 %ext = sext <2 x i16> %sel to <2 x i32> 134 %ext = sext <2 x i16> %sel to <2 x i32>
137 ret <2 x i32> %ext 135 ret <2 x i32> %ext
138 } 136 }
139 137
140 define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) { 138 define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) {
141 ; CHECK-LABEL: @trunc_sel_equal_sext( 139 ; CHECK-LABEL: @trunc_sel_equal_sext(
142 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %a, 16 140 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A:%.*]], 16
143 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i32 [[SEXT]], 16 141 ; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 16
144 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42 142 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP2]], i32 42
145 ; CHECK-NEXT: ret i32 [[EXT]] 143 ; CHECK-NEXT: ret i32 [[EXT]]
146 ; 144 ;
147 %trunc = trunc i32 %a to i16 145 %trunc = trunc i32 %a to i16
148 %sel = select i1 %cmp, i16 %trunc, i16 42 146 %sel = select i1 %cmp, i16 %trunc, i16 42
149 %ext = sext i16 %sel to i32 147 %ext = sext i16 %sel to i32
150 ret i32 %ext 148 ret i32 %ext
151 } 149 }
152 150
153 define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) { 151 define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
154 ; CHECK-LABEL: @trunc_sel_equal_sext_vec( 152 ; CHECK-LABEL: @trunc_sel_equal_sext_vec(
155 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> %a, <i32 16, i32 16> 153 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[A:%.*]], <i32 16, i32 16>
156 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16> 154 ; CHECK-NEXT: [[TMP2:%.*]] = ashr exact <2 x i32> [[TMP1]], <i32 16, i32 16>
157 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43> 155 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP2]], <2 x i32> <i32 42, i32 43>
158 ; CHECK-NEXT: ret <2 x i32> [[EXT]] 156 ; CHECK-NEXT: ret <2 x i32> [[EXT]]
159 ; 157 ;
160 %trunc = trunc <2 x i32> %a to <2 x i16> 158 %trunc = trunc <2 x i32> %a to <2 x i16>
161 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43> 159 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
162 %ext = sext <2 x i16> %sel to <2 x i32> 160 %ext = sext <2 x i16> %sel to <2 x i32>
163 ret <2 x i32> %ext 161 ret <2 x i32> %ext
164 } 162 }
165 163
166 define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) { 164 define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) {
167 ; CHECK-LABEL: @trunc_sel_larger_zext( 165 ; CHECK-LABEL: @trunc_sel_larger_zext(
168 ; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 %a, 65535 166 ; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 [[A:%.*]], 65535
169 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64 167 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64
170 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42 168 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i64 [[TMP1]], i64 42
171 ; CHECK-NEXT: ret i64 [[EXT]] 169 ; CHECK-NEXT: ret i64 [[EXT]]
172 ; 170 ;
173 %trunc = trunc i32 %a to i16 171 %trunc = trunc i32 %a to i16
174 %sel = select i1 %cmp, i16 %trunc, i16 42 172 %sel = select i1 %cmp, i16 %trunc, i16 42
175 %ext = zext i16 %sel to i64 173 %ext = zext i16 %sel to i64
176 ret i64 %ext 174 ret i64 %ext
177 } 175 }
178 176
179 define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) { 177 define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
180 ; CHECK-LABEL: @trunc_sel_larger_zext_vec( 178 ; CHECK-LABEL: @trunc_sel_larger_zext_vec(
181 ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535> 179 ; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and <2 x i32> [[A:%.*]], <i32 65535, i32 65535>
182 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> 180 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[TRUNC_MASK]] to <2 x i64>
183 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP2]], <2 x i64> <i64 42, i64 43> 181 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
184 ; CHECK-NEXT: ret <2 x i64> [[EXT]] 182 ; CHECK-NEXT: ret <2 x i64> [[EXT]]
185 ; 183 ;
186 %trunc = trunc <2 x i32> %a to <2 x i16> 184 %trunc = trunc <2 x i32> %a to <2 x i16>
187 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43> 185 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
188 %ext = zext <2 x i16> %sel to <2 x i64> 186 %ext = zext <2 x i16> %sel to <2 x i64>
189 ret <2 x i64> %ext 187 ret <2 x i64> %ext
190 } 188 }
191 189
192 define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) { 190 define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) {
193 ; CHECK-LABEL: @trunc_sel_smaller_zext( 191 ; CHECK-LABEL: @trunc_sel_smaller_zext(
194 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 %a to i32 192 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A:%.*]] to i32
195 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65535 193 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65535
196 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP2]], i32 42 194 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP2]], i32 42
197 ; CHECK-NEXT: ret i32 [[EXT]] 195 ; CHECK-NEXT: ret i32 [[EXT]]
198 ; 196 ;
199 %trunc = trunc i64 %a to i16 197 %trunc = trunc i64 %a to i16
200 %sel = select i1 %cmp, i16 %trunc, i16 42 198 %sel = select i1 %cmp, i16 %trunc, i16 42
201 %ext = zext i16 %sel to i32 199 %ext = zext i16 %sel to i32
202 ret i32 %ext 200 ret i32 %ext
203 } 201 }
204 202
205 define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) { 203 define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) {
206 ; CHECK-LABEL: @trunc_sel_smaller_zext_vec( 204 ; CHECK-LABEL: @trunc_sel_smaller_zext_vec(
207 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32> 205 ; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32>
208 ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TRUNC]], <i32 65535, i32 65535> 206 ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 65535, i32 65535>
209 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43> 207 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP2]], <2 x i32> <i32 42, i32 43>
210 ; CHECK-NEXT: ret <2 x i32> [[EXT]] 208 ; CHECK-NEXT: ret <2 x i32> [[EXT]]
211 ; 209 ;
212 %trunc = trunc <2 x i64> %a to <2 x i16> 210 %trunc = trunc <2 x i64> %a to <2 x i16>
213 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43> 211 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
214 %ext = zext <2 x i16> %sel to <2 x i32> 212 %ext = zext <2 x i16> %sel to <2 x i32>
215 ret <2 x i32> %ext 213 ret <2 x i32> %ext
216 } 214 }
217 215
218 define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) { 216 define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) {
219 ; CHECK-LABEL: @trunc_sel_equal_zext( 217 ; CHECK-LABEL: @trunc_sel_equal_zext(
220 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, 65535 218 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 65535
221 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42 219 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], i32 [[TMP1]], i32 42
222 ; CHECK-NEXT: ret i32 [[EXT]] 220 ; CHECK-NEXT: ret i32 [[EXT]]
223 ; 221 ;
224 %trunc = trunc i32 %a to i16 222 %trunc = trunc i32 %a to i16
225 %sel = select i1 %cmp, i16 %trunc, i16 42 223 %sel = select i1 %cmp, i16 %trunc, i16 42
226 %ext = zext i16 %sel to i32 224 %ext = zext i16 %sel to i32
227 ret i32 %ext 225 ret i32 %ext
228 } 226 }
229 227
230 define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) { 228 define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
231 ; CHECK-LABEL: @trunc_sel_equal_zext_vec( 229 ; CHECK-LABEL: @trunc_sel_equal_zext_vec(
232 ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535> 230 ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 65535, i32 65535>
233 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43> 231 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
234 ; CHECK-NEXT: ret <2 x i32> [[EXT]] 232 ; CHECK-NEXT: ret <2 x i32> [[EXT]]
235 ; 233 ;
236 %trunc = trunc <2 x i32> %a to <2 x i16> 234 %trunc = trunc <2 x i32> %a to <2 x i16>
237 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43> 235 %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
238 %ext = zext <2 x i16> %sel to <2 x i32> 236 %ext = zext <2 x i16> %sel to <2 x i32>
239 ret <2 x i32> %ext 237 ret <2 x i32> %ext
240 } 238 }
241 239
242 define double @trunc_sel_larger_fpext(float %a, i1 %cmp) { 240 define double @trunc_sel_larger_fpext(float %a, i1 %cmp) {
243 ; CHECK-LABEL: @trunc_sel_larger_fpext( 241 ; CHECK-LABEL: @trunc_sel_larger_fpext(
244 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float %a to half 242 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float [[A:%.*]] to half
245 ; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to double 243 ; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to double
246 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, double [[TMP1]], double 4.200000e+01 244 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], double [[TMP1]], double 4.200000e+01
247 ; CHECK-NEXT: ret double [[EXT]] 245 ; CHECK-NEXT: ret double [[EXT]]
248 ; 246 ;
249 %trunc = fptrunc float %a to half 247 %trunc = fptrunc float %a to half
250 %sel = select i1 %cmp, half %trunc, half 42.0 248 %sel = select i1 %cmp, half %trunc, half 42.0
251 %ext = fpext half %sel to double 249 %ext = fpext half %sel to double
252 ret double %ext 250 ret double %ext
253 } 251 }
254 252
255 define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) { 253 define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
256 ; CHECK-LABEL: @trunc_sel_larger_fpext_vec( 254 ; CHECK-LABEL: @trunc_sel_larger_fpext_vec(
257 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half> 255 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> [[A:%.*]] to <2 x half>
258 ; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double> 256 ; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double>
259 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01> 257 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01>
260 ; CHECK-NEXT: ret <2 x double> [[EXT]] 258 ; CHECK-NEXT: ret <2 x double> [[EXT]]
261 ; 259 ;
262 %trunc = fptrunc <2 x float> %a to <2 x half> 260 %trunc = fptrunc <2 x float> %a to <2 x half>
263 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0> 261 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
264 %ext = fpext <2 x half> %sel to <2 x double> 262 %ext = fpext <2 x half> %sel to <2 x double>
265 ret <2 x double> %ext 263 ret <2 x double> %ext
266 } 264 }
267 265
268 define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) { 266 define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) {
269 ; CHECK-LABEL: @trunc_sel_smaller_fpext( 267 ; CHECK-LABEL: @trunc_sel_smaller_fpext(
270 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double %a to half 268 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[A:%.*]] to half
271 ; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float 269 ; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
272 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01 270 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], float [[TMP1]], float 4.200000e+01
273 ; CHECK-NEXT: ret float [[EXT]] 271 ; CHECK-NEXT: ret float [[EXT]]
274 ; 272 ;
275 %trunc = fptrunc double %a to half 273 %trunc = fptrunc double %a to half
276 %sel = select i1 %cmp, half %trunc, half 42.0 274 %sel = select i1 %cmp, half %trunc, half 42.0
277 %ext = fpext half %sel to float 275 %ext = fpext half %sel to float
278 ret float %ext 276 ret float %ext
279 } 277 }
280 278
281 define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) { 279 define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) {
282 ; CHECK-LABEL: @trunc_sel_smaller_fpext_vec( 280 ; CHECK-LABEL: @trunc_sel_smaller_fpext_vec(
283 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x double> %a to <2 x half> 281 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x double> [[A:%.*]] to <2 x half>
284 ; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float> 282 ; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
285 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01> 283 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
286 ; CHECK-NEXT: ret <2 x float> [[EXT]] 284 ; CHECK-NEXT: ret <2 x float> [[EXT]]
287 ; 285 ;
288 %trunc = fptrunc <2 x double> %a to <2 x half> 286 %trunc = fptrunc <2 x double> %a to <2 x half>
289 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0> 287 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
290 %ext = fpext <2 x half> %sel to <2 x float> 288 %ext = fpext <2 x half> %sel to <2 x float>
291 ret <2 x float> %ext 289 ret <2 x float> %ext
292 } 290 }
293 291
294 define float @trunc_sel_equal_fpext(float %a, i1 %cmp) { 292 define float @trunc_sel_equal_fpext(float %a, i1 %cmp) {
295 ; CHECK-LABEL: @trunc_sel_equal_fpext( 293 ; CHECK-LABEL: @trunc_sel_equal_fpext(
296 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float %a to half 294 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float [[A:%.*]] to half
297 ; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float 295 ; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
298 ; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01 296 ; CHECK-NEXT: [[EXT:%.*]] = select i1 [[CMP:%.*]], float [[TMP1]], float 4.200000e+01
299 ; CHECK-NEXT: ret float [[EXT]] 297 ; CHECK-NEXT: ret float [[EXT]]
300 ; 298 ;
301 %trunc = fptrunc float %a to half 299 %trunc = fptrunc float %a to half
302 %sel = select i1 %cmp, half %trunc, half 42.0 300 %sel = select i1 %cmp, half %trunc, half 42.0
303 %ext = fpext half %sel to float 301 %ext = fpext half %sel to float
304 ret float %ext 302 ret float %ext
305 } 303 }
306 304
307 define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) { 305 define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
308 ; CHECK-LABEL: @trunc_sel_equal_fpext_vec( 306 ; CHECK-LABEL: @trunc_sel_equal_fpext_vec(
309 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half> 307 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> [[A:%.*]] to <2 x half>
310 ; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float> 308 ; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
311 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01> 309 ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> [[CMP:%.*]], <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
312 ; CHECK-NEXT: ret <2 x float> [[EXT]] 310 ; CHECK-NEXT: ret <2 x float> [[EXT]]
313 ; 311 ;
314 %trunc = fptrunc <2 x float> %a to <2 x half> 312 %trunc = fptrunc <2 x float> %a to <2 x half>
315 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0> 313 %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
316 %ext = fpext <2 x half> %sel to <2 x float> 314 %ext = fpext <2 x half> %sel to <2 x float>
317 ret <2 x float> %ext 315 ret <2 x float> %ext
318 } 316 }
319 317
320 define i32 @test_sext1(i1 %cca, i1 %ccb) { 318 define i32 @test_sext1(i1 %cca, i1 %ccb) {
321 ; CHECK-LABEL: @test_sext1( 319 ; CHECK-LABEL: @test_sext1(
322 ; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca 320 ; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[CCB:%.*]], [[CCA:%.*]]
323 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32 321 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
324 ; CHECK-NEXT: ret i32 [[R]] 322 ; CHECK-NEXT: ret i32 [[R]]
325 ; 323 ;
326 %ccax = sext i1 %cca to i32 324 %ccax = sext i1 %cca to i32
327 %r = select i1 %ccb, i32 %ccax, i32 0 325 %r = select i1 %ccb, i32 %ccax, i32 0
328 ret i32 %r 326 ret i32 %r
329 } 327 }
330 328
331 define i32 @test_sext2(i1 %cca, i1 %ccb) { 329 define i32 @test_sext2(i1 %cca, i1 %ccb) {
332 ; CHECK-LABEL: @test_sext2( 330 ; CHECK-LABEL: @test_sext2(
333 ; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 %ccb, %cca 331 ; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[CCB:%.*]], [[CCA:%.*]]
334 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32 332 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
335 ; CHECK-NEXT: ret i32 [[R]] 333 ; CHECK-NEXT: ret i32 [[R]]
336 ; 334 ;
337 %ccax = sext i1 %cca to i32 335 %ccax = sext i1 %cca to i32
338 %r = select i1 %ccb, i32 -1, i32 %ccax 336 %r = select i1 %ccb, i32 -1, i32 %ccax
339 ret i32 %r 337 ret i32 %r
340 } 338 }
341 339
342 define i32 @test_sext3(i1 %cca, i1 %ccb) { 340 define i32 @test_sext3(i1 %cca, i1 %ccb) {
343 ; CHECK-LABEL: @test_sext3( 341 ; CHECK-LABEL: @test_sext3(
344 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true 342 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
345 ; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 [[NOT_CCB]], %cca 343 ; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[NOT_CCB]], [[CCA:%.*]]
346 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32 344 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
347 ; CHECK-NEXT: ret i32 [[R]] 345 ; CHECK-NEXT: ret i32 [[R]]
348 ; 346 ;
349 %ccax = sext i1 %cca to i32 347 %ccax = sext i1 %cca to i32
350 %r = select i1 %ccb, i32 0, i32 %ccax 348 %r = select i1 %ccb, i32 0, i32 %ccax
351 ret i32 %r 349 ret i32 %r
352 } 350 }
353 351
354 define i32 @test_sext4(i1 %cca, i1 %ccb) { 352 define i32 @test_sext4(i1 %cca, i1 %ccb) {
355 ; CHECK-LABEL: @test_sext4( 353 ; CHECK-LABEL: @test_sext4(
356 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true 354 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
357 ; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 [[NOT_CCB]], %cca 355 ; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[NOT_CCB]], [[CCA:%.*]]
358 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[FOLD_R]] to i32 356 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[NARROW]] to i32
359 ; CHECK-NEXT: ret i32 [[R]] 357 ; CHECK-NEXT: ret i32 [[R]]
360 ; 358 ;
361 %ccax = sext i1 %cca to i32 359 %ccax = sext i1 %cca to i32
362 %r = select i1 %ccb, i32 %ccax, i32 -1 360 %r = select i1 %ccb, i32 %ccax, i32 -1
363 ret i32 %r 361 ret i32 %r
364 } 362 }
365 363
366 define i32 @test_zext1(i1 %cca, i1 %ccb) { 364 define i32 @test_zext1(i1 %cca, i1 %ccb) {
367 ; CHECK-LABEL: @test_zext1( 365 ; CHECK-LABEL: @test_zext1(
368 ; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca 366 ; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[CCB:%.*]], [[CCA:%.*]]
369 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32 367 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
370 ; CHECK-NEXT: ret i32 [[R]] 368 ; CHECK-NEXT: ret i32 [[R]]
371 ; 369 ;
372 %ccax = zext i1 %cca to i32 370 %ccax = zext i1 %cca to i32
373 %r = select i1 %ccb, i32 %ccax, i32 0 371 %r = select i1 %ccb, i32 %ccax, i32 0
374 ret i32 %r 372 ret i32 %r
375 } 373 }
376 374
377 define i32 @test_zext2(i1 %cca, i1 %ccb) { 375 define i32 @test_zext2(i1 %cca, i1 %ccb) {
378 ; CHECK-LABEL: @test_zext2( 376 ; CHECK-LABEL: @test_zext2(
379 ; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 %ccb, %cca 377 ; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[CCB:%.*]], [[CCA:%.*]]
380 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32 378 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
381 ; CHECK-NEXT: ret i32 [[R]] 379 ; CHECK-NEXT: ret i32 [[R]]
382 ; 380 ;
383 %ccax = zext i1 %cca to i32 381 %ccax = zext i1 %cca to i32
384 %r = select i1 %ccb, i32 1, i32 %ccax 382 %r = select i1 %ccb, i32 1, i32 %ccax
385 ret i32 %r 383 ret i32 %r
386 } 384 }
387 385
388 define i32 @test_zext3(i1 %cca, i1 %ccb) { 386 define i32 @test_zext3(i1 %cca, i1 %ccb) {
389 ; CHECK-LABEL: @test_zext3( 387 ; CHECK-LABEL: @test_zext3(
390 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true 388 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
391 ; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 [[NOT_CCB]], %cca 389 ; CHECK-NEXT: [[NARROW:%.*]] = and i1 [[NOT_CCB]], [[CCA:%.*]]
392 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32 390 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
393 ; CHECK-NEXT: ret i32 [[R]] 391 ; CHECK-NEXT: ret i32 [[R]]
394 ; 392 ;
395 %ccax = zext i1 %cca to i32 393 %ccax = zext i1 %cca to i32
396 %r = select i1 %ccb, i32 0, i32 %ccax 394 %r = select i1 %ccb, i32 0, i32 %ccax
397 ret i32 %r 395 ret i32 %r
398 } 396 }
399 397
400 define i32 @test_zext4(i1 %cca, i1 %ccb) { 398 define i32 @test_zext4(i1 %cca, i1 %ccb) {
401 ; CHECK-LABEL: @test_zext4( 399 ; CHECK-LABEL: @test_zext4(
402 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 %ccb, true 400 ; CHECK-NEXT: [[NOT_CCB:%.*]] = xor i1 [[CCB:%.*]], true
403 ; CHECK-NEXT: [[FOLD_R:%.*]] = or i1 [[NOT_CCB]], %cca 401 ; CHECK-NEXT: [[NARROW:%.*]] = or i1 [[NOT_CCB]], [[CCA:%.*]]
404 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[FOLD_R]] to i32 402 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
405 ; CHECK-NEXT: ret i32 [[R]] 403 ; CHECK-NEXT: ret i32 [[R]]
406 ; 404 ;
407 %ccax = zext i1 %cca to i32 405 %ccax = zext i1 %cca to i32
408 %r = select i1 %ccb, i32 %ccax, i32 1 406 %r = select i1 %ccb, i32 %ccax, i32 1
409 ret i32 %r 407 ret i32 %r
410 } 408 }
411 409
412 define i32 @test_negative_sext(i1 %a, i1 %cc) { 410 define i32 @test_negative_sext(i1 %a, i1 %cc) {
413 ; CHECK-LABEL: @test_negative_sext( 411 ; CHECK-LABEL: @test_negative_sext(
414 ; CHECK-NEXT: [[A_EXT:%.*]] = sext i1 %a to i32 412 ; CHECK-NEXT: [[A_EXT:%.*]] = sext i1 [[A:%.*]] to i32
415 ; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 1 413 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 1
416 ; CHECK-NEXT: ret i32 [[R]] 414 ; CHECK-NEXT: ret i32 [[R]]
417 ; 415 ;
418 %a.ext = sext i1 %a to i32 416 %a.ext = sext i1 %a to i32
419 %r = select i1 %cc, i32 %a.ext, i32 1 417 %r = select i1 %cc, i32 %a.ext, i32 1
420 ret i32 %r 418 ret i32 %r
421 } 419 }
422 420
423 define i32 @test_negative_zext(i1 %a, i1 %cc) { 421 define i32 @test_negative_zext(i1 %a, i1 %cc) {
424 ; CHECK-LABEL: @test_negative_zext( 422 ; CHECK-LABEL: @test_negative_zext(
425 ; CHECK-NEXT: [[A_EXT:%.*]] = zext i1 %a to i32 423 ; CHECK-NEXT: [[A_EXT:%.*]] = zext i1 [[A:%.*]] to i32
426 ; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 -1 424 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 -1
427 ; CHECK-NEXT: ret i32 [[R]] 425 ; CHECK-NEXT: ret i32 [[R]]
428 ; 426 ;
429 %a.ext = zext i1 %a to i32 427 %a.ext = zext i1 %a to i32
430 %r = select i1 %cc, i32 %a.ext, i32 -1 428 %r = select i1 %cc, i32 %a.ext, i32 -1
431 ret i32 %r 429 ret i32 %r
432 } 430 }
433 431
434 define i32 @test_bits_sext(i8 %a, i1 %cc) { 432 define i32 @test_bits_sext(i8 %a, i1 %cc) {
435 ; CHECK-LABEL: @test_bits_sext( 433 ; CHECK-LABEL: @test_bits_sext(
436 ; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 %a to i32 434 ; CHECK-NEXT: [[A_EXT:%.*]] = sext i8 [[A:%.*]] to i32
437 ; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 -128 435 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 -128
438 ; CHECK-NEXT: ret i32 [[R]] 436 ; CHECK-NEXT: ret i32 [[R]]
439 ; 437 ;
440 %a.ext = sext i8 %a to i32 438 %a.ext = sext i8 %a to i32
441 %r = select i1 %cc, i32 %a.ext, i32 -128 439 %r = select i1 %cc, i32 %a.ext, i32 -128
442 ret i32 %r 440 ret i32 %r
443 } 441 }
444 442
445 define i32 @test_bits_zext(i8 %a, i1 %cc) { 443 define i32 @test_bits_zext(i8 %a, i1 %cc) {
446 ; CHECK-LABEL: @test_bits_zext( 444 ; CHECK-LABEL: @test_bits_zext(
447 ; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 %a to i32 445 ; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 [[A:%.*]] to i32
448 ; CHECK-NEXT: [[R:%.*]] = select i1 %cc, i32 [[A_EXT]], i32 255 446 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CC:%.*]], i32 [[A_EXT]], i32 255
449 ; CHECK-NEXT: ret i32 [[R]] 447 ; CHECK-NEXT: ret i32 [[R]]
450 ; 448 ;
451 %a.ext = zext i8 %a to i32 449 %a.ext = zext i8 %a to i32
452 %r = select i1 %cc, i32 %a.ext, i32 255 450 %r = select i1 %cc, i32 %a.ext, i32 255
453 ret i32 %r 451 ret i32 %r
454 } 452 }
455 453
456 define i32 @test_op_op(i32 %a, i32 %b, i32 %c) { 454 define i32 @test_op_op(i32 %a, i32 %b, i32 %c) {
457 ; CHECK-LABEL: @test_op_op( 455 ; CHECK-LABEL: @test_op_op(
458 ; CHECK-NEXT: [[CCA:%.*]] = icmp sgt i32 %a, 0 456 ; CHECK-NEXT: [[CCA:%.*]] = icmp sgt i32 [[A:%.*]], 0
459 ; CHECK-NEXT: [[CCB:%.*]] = icmp sgt i32 %b, 0 457 ; CHECK-NEXT: [[CCB:%.*]] = icmp sgt i32 [[B:%.*]], 0
460 ; CHECK-NEXT: [[CCC:%.*]] = icmp sgt i32 %c, 0 458 ; CHECK-NEXT: [[CCC:%.*]] = icmp sgt i32 [[C:%.*]], 0
461 ; CHECK-NEXT: [[R_V:%.*]] = select i1 [[CCC]], i1 [[CCA]], i1 [[CCB]] 459 ; CHECK-NEXT: [[R_V:%.*]] = select i1 [[CCC]], i1 [[CCA]], i1 [[CCB]]
462 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[R:%.*]].v to i32 460 ; CHECK-NEXT: [[R:%.*]] = sext i1 [[R_V]] to i32
463 ; CHECK-NEXT: ret i32 [[R]] 461 ; CHECK-NEXT: ret i32 [[R]]
464 ; 462 ;
465 %cca = icmp sgt i32 %a, 0 463 %cca = icmp sgt i32 %a, 0
466 %ccax = sext i1 %cca to i32 464 %ccax = sext i1 %cca to i32
467 %ccb = icmp sgt i32 %b, 0 465 %ccb = icmp sgt i32 %b, 0
471 ret i32 %r 469 ret i32 %r
472 } 470 }
473 471
474 define <2 x i32> @test_vectors_sext(<2 x i1> %cca, <2 x i1> %ccb) { 472 define <2 x i32> @test_vectors_sext(<2 x i1> %cca, <2 x i1> %ccb) {
475 ; CHECK-LABEL: @test_vectors_sext( 473 ; CHECK-LABEL: @test_vectors_sext(
476 ; CHECK-NEXT: [[FOLD_R:%.*]] = and <2 x i1> %ccb, %cca 474 ; CHECK-NEXT: [[NARROW:%.*]] = and <2 x i1> [[CCB:%.*]], [[CCA:%.*]]
477 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[FOLD_R]] to <2 x i32> 475 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
478 ; CHECK-NEXT: ret <2 x i32> [[R]] 476 ; CHECK-NEXT: ret <2 x i32> [[R]]
479 ; 477 ;
480 %ccax = sext <2 x i1> %cca to <2 x i32> 478 %ccax = sext <2 x i1> %cca to <2 x i32>
481 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0> 479 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
482 ret <2 x i32> %r 480 ret <2 x i32> %r
483 } 481 }
484 482
485 define <2 x i32> @test_vectors_sext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) { 483 define <2 x i32> @test_vectors_sext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
486 ; CHECK-LABEL: @test_vectors_sext_nonsplat( 484 ; CHECK-LABEL: @test_vectors_sext_nonsplat(
487 ; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> %ccb, <2 x i1> %cca, <2 x i1> <i1 false, i1 true> 485 ; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 false, i1 true>
488 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32> 486 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
489 ; CHECK-NEXT: ret <2 x i32> [[R]] 487 ; CHECK-NEXT: ret <2 x i32> [[R]]
490 ; 488 ;
491 %ccax = sext <2 x i1> %cca to <2 x i32> 489 %ccax = sext <2 x i1> %cca to <2 x i32>
492 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 -1> 490 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 -1>
493 ret <2 x i32> %r 491 ret <2 x i32> %r
494 } 492 }
495 493
496 define <2 x i32> @test_vectors_zext(<2 x i1> %cca, <2 x i1> %ccb) { 494 define <2 x i32> @test_vectors_zext(<2 x i1> %cca, <2 x i1> %ccb) {
497 ; CHECK-LABEL: @test_vectors_zext( 495 ; CHECK-LABEL: @test_vectors_zext(
498 ; CHECK-NEXT: [[FOLD_R:%.*]] = and <2 x i1> %ccb, %cca 496 ; CHECK-NEXT: [[NARROW:%.*]] = and <2 x i1> [[CCB:%.*]], [[CCA:%.*]]
499 ; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[FOLD_R]] to <2 x i32> 497 ; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
500 ; CHECK-NEXT: ret <2 x i32> [[R]] 498 ; CHECK-NEXT: ret <2 x i32> [[R]]
501 ; 499 ;
502 %ccax = zext <2 x i1> %cca to <2 x i32> 500 %ccax = zext <2 x i1> %cca to <2 x i32>
503 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0> 501 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
504 ret <2 x i32> %r 502 ret <2 x i32> %r
505 } 503 }
506 504
507 define <2 x i32> @test_vectors_zext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) { 505 define <2 x i32> @test_vectors_zext_nonsplat(<2 x i1> %cca, <2 x i1> %ccb) {
508 ; CHECK-LABEL: @test_vectors_zext_nonsplat( 506 ; CHECK-LABEL: @test_vectors_zext_nonsplat(
509 ; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> %ccb, <2 x i1> %cca, <2 x i1> <i1 true, i1 false> 507 ; CHECK-NEXT: [[NARROW:%.*]] = select <2 x i1> [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> <i1 true, i1 false>
510 ; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32> 508 ; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
511 ; CHECK-NEXT: ret <2 x i32> [[R]] 509 ; CHECK-NEXT: ret <2 x i32> [[R]]
512 ; 510 ;
513 %ccax = zext <2 x i1> %cca to <2 x i32> 511 %ccax = zext <2 x i1> %cca to <2 x i32>
514 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 1, i32 0> 512 %r = select <2 x i1> %ccb, <2 x i32> %ccax, <2 x i32> <i32 1, i32 0>
515 ret <2 x i32> %r 513 ret <2 x i32> %r
516 } 514 }
517 515
518 define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) { 516 define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
519 ; CHECK-LABEL: @scalar_select_of_vectors_sext( 517 ; CHECK-LABEL: @scalar_select_of_vectors_sext(
520 ; CHECK-NEXT: [[FOLD_R:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer 518 ; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer
521 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[FOLD_R]] to <2 x i32> 519 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
522 ; CHECK-NEXT: ret <2 x i32> [[R]] 520 ; CHECK-NEXT: ret <2 x i32> [[R]]
523 ; 521 ;
524 %ccax = sext <2 x i1> %cca to <2 x i32> 522 %ccax = sext <2 x i1> %cca to <2 x i32>
525 %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0> 523 %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
526 ret <2 x i32> %r 524 ret <2 x i32> %r
527 } 525 }
528 526
529 define <2 x i32> @scalar_select_of_vectors_zext(<2 x i1> %cca, i1 %ccb) { 527 define <2 x i32> @scalar_select_of_vectors_zext(<2 x i1> %cca, i1 %ccb) {
530 ; CHECK-LABEL: @scalar_select_of_vectors_zext( 528 ; CHECK-LABEL: @scalar_select_of_vectors_zext(
531 ; CHECK-NEXT: [[FOLD_R:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer 529 ; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CCB:%.*]], <2 x i1> [[CCA:%.*]], <2 x i1> zeroinitializer
532 ; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[FOLD_R]] to <2 x i32> 530 ; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[NARROW]] to <2 x i32>
533 ; CHECK-NEXT: ret <2 x i32> [[R]] 531 ; CHECK-NEXT: ret <2 x i32> [[R]]
534 ; 532 ;
535 %ccax = zext <2 x i1> %cca to <2 x i32> 533 %ccax = zext <2 x i1> %cca to <2 x i32>
536 %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0> 534 %r = select i1 %ccb, <2 x i32> %ccax, <2 x i32> <i32 0, i32 0>
537 ret <2 x i32> %r 535 ret <2 x i32> %r
538 } 536 }
539 537
540 define i32 @sext_true_val_must_be_all_ones(i1 %x) { 538 define i32 @sext_true_val_must_be_all_ones(i1 %x) {
541 ; CHECK-LABEL: @sext_true_val_must_be_all_ones( 539 ; CHECK-LABEL: @sext_true_val_must_be_all_ones(
542 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 -1, i32 42, !prof !0 540 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 -1, i32 42, !prof !0
543 ; CHECK-NEXT: ret i32 [[SEL]] 541 ; CHECK-NEXT: ret i32 [[SEL]]
544 ; 542 ;
545 %ext = sext i1 %x to i32 543 %ext = sext i1 %x to i32
546 %sel = select i1 %x, i32 %ext, i32 42, !prof !0 544 %sel = select i1 %x, i32 %ext, i32 42, !prof !0
547 ret i32 %sel 545 ret i32 %sel
548 } 546 }
549 547
550 define <2 x i32> @sext_true_val_must_be_all_ones_vec(<2 x i1> %x) { 548 define <2 x i32> @sext_true_val_must_be_all_ones_vec(<2 x i1> %x) {
551 ; CHECK-LABEL: @sext_true_val_must_be_all_ones_vec( 549 ; CHECK-LABEL: @sext_true_val_must_be_all_ones_vec(
552 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 42, i32 12>, !prof !0 550 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 42, i32 12>, !prof !0
553 ; CHECK-NEXT: ret <2 x i32> [[SEL]] 551 ; CHECK-NEXT: ret <2 x i32> [[SEL]]
554 ; 552 ;
555 %ext = sext <2 x i1> %x to <2 x i32> 553 %ext = sext <2 x i1> %x to <2 x i32>
556 %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0 554 %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0
557 ret <2 x i32> %sel 555 ret <2 x i32> %sel
558 } 556 }
559 557
560 define i32 @zext_true_val_must_be_one(i1 %x) { 558 define i32 @zext_true_val_must_be_one(i1 %x) {
561 ; CHECK-LABEL: @zext_true_val_must_be_one( 559 ; CHECK-LABEL: @zext_true_val_must_be_one(
562 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 1, i32 42, !prof !0 560 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 1, i32 42, !prof !0
563 ; CHECK-NEXT: ret i32 [[SEL]] 561 ; CHECK-NEXT: ret i32 [[SEL]]
564 ; 562 ;
565 %ext = zext i1 %x to i32 563 %ext = zext i1 %x to i32
566 %sel = select i1 %x, i32 %ext, i32 42, !prof !0 564 %sel = select i1 %x, i32 %ext, i32 42, !prof !0
567 ret i32 %sel 565 ret i32 %sel
568 } 566 }
569 567
570 define <2 x i32> @zext_true_val_must_be_one_vec(<2 x i1> %x) { 568 define <2 x i32> @zext_true_val_must_be_one_vec(<2 x i1> %x) {
571 ; CHECK-LABEL: @zext_true_val_must_be_one_vec( 569 ; CHECK-LABEL: @zext_true_val_must_be_one_vec(
572 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 42, i32 12>, !prof !0 570 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 1, i32 1>, <2 x i32> <i32 42, i32 12>, !prof !0
573 ; CHECK-NEXT: ret <2 x i32> [[SEL]] 571 ; CHECK-NEXT: ret <2 x i32> [[SEL]]
574 ; 572 ;
575 %ext = zext <2 x i1> %x to <2 x i32> 573 %ext = zext <2 x i1> %x to <2 x i32>
576 %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0 574 %sel = select <2 x i1> %x, <2 x i32> %ext, <2 x i32> <i32 42, i32 12>, !prof !0
577 ret <2 x i32> %sel 575 ret <2 x i32> %sel
578 } 576 }
579 577
580 define i32 @sext_false_val_must_be_zero(i1 %x) { 578 define i32 @sext_false_val_must_be_zero(i1 %x) {
581 ; CHECK-LABEL: @sext_false_val_must_be_zero( 579 ; CHECK-LABEL: @sext_false_val_must_be_zero(
582 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 42, i32 0, !prof !0 580 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 42, i32 0, !prof !0
583 ; CHECK-NEXT: ret i32 [[SEL]] 581 ; CHECK-NEXT: ret i32 [[SEL]]
584 ; 582 ;
585 %ext = sext i1 %x to i32 583 %ext = sext i1 %x to i32
586 %sel = select i1 %x, i32 42, i32 %ext, !prof !0 584 %sel = select i1 %x, i32 42, i32 %ext, !prof !0
587 ret i32 %sel 585 ret i32 %sel
588 } 586 }
589 587
590 define <2 x i32> @sext_false_val_must_be_zero_vec(<2 x i1> %x) { 588 define <2 x i32> @sext_false_val_must_be_zero_vec(<2 x i1> %x) {
591 ; CHECK-LABEL: @sext_false_val_must_be_zero_vec( 589 ; CHECK-LABEL: @sext_false_val_must_be_zero_vec(
592 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0 590 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0
593 ; CHECK-NEXT: ret <2 x i32> [[SEL]] 591 ; CHECK-NEXT: ret <2 x i32> [[SEL]]
594 ; 592 ;
595 %ext = sext <2 x i1> %x to <2 x i32> 593 %ext = sext <2 x i1> %x to <2 x i32>
596 %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0 594 %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0
597 ret <2 x i32> %sel 595 ret <2 x i32> %sel
598 } 596 }
599 597
600 define i32 @zext_false_val_must_be_zero(i1 %x) { 598 define i32 @zext_false_val_must_be_zero(i1 %x) {
601 ; CHECK-LABEL: @zext_false_val_must_be_zero( 599 ; CHECK-LABEL: @zext_false_val_must_be_zero(
602 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %x, i32 42, i32 0, !prof !0 600 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[X:%.*]], i32 42, i32 0, !prof !0
603 ; CHECK-NEXT: ret i32 [[SEL]] 601 ; CHECK-NEXT: ret i32 [[SEL]]
604 ; 602 ;
605 %ext = zext i1 %x to i32 603 %ext = zext i1 %x to i32
606 %sel = select i1 %x, i32 42, i32 %ext, !prof !0 604 %sel = select i1 %x, i32 42, i32 %ext, !prof !0
607 ret i32 %sel 605 ret i32 %sel
608 } 606 }
609 607
610 define <2 x i32> @zext_false_val_must_be_zero_vec(<2 x i1> %x) { 608 define <2 x i32> @zext_false_val_must_be_zero_vec(<2 x i1> %x) {
611 ; CHECK-LABEL: @zext_false_val_must_be_zero_vec( 609 ; CHECK-LABEL: @zext_false_val_must_be_zero_vec(
612 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0 610 ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[X:%.*]], <2 x i32> <i32 42, i32 12>, <2 x i32> zeroinitializer, !prof !0
613 ; CHECK-NEXT: ret <2 x i32> [[SEL]] 611 ; CHECK-NEXT: ret <2 x i32> [[SEL]]
614 ; 612 ;
615 %ext = zext <2 x i1> %x to <2 x i32> 613 %ext = zext <2 x i1> %x to <2 x i32>
616 %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0 614 %sel = select <2 x i1> %x, <2 x i32> <i32 42, i32 12>, <2 x i32> %ext, !prof !0
617 ret <2 x i32> %sel 615 ret <2 x i32> %sel