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diff llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents 79ff65ed7e25
children
line wrap: on
line diff
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll	Wed Nov 09 17:47:54 2022 +0900
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll	Fri Aug 18 09:04:13 2023 +0900
@@ -8,10 +8,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_kernel void @kernel_ieee_mode_default() #0 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -23,10 +23,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_kernel void @kernel_ieee_mode_on() #1 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -38,10 +38,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_kernel void @kernel_ieee_mode_off() #2 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -53,10 +53,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define void @func_ieee_mode_default() #0 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -68,10 +68,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define void @func_ieee_mode_on() #1 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -83,10 +83,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
 ; GCN-NOT: v_mul_f32
 define void @func_ieee_mode_off() #2 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -98,10 +98,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_cs void @cs_ieee_mode_default() #0 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -113,10 +113,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_cs void @cs_ieee_mode_on() #1 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -128,10 +128,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_cs void @cs_ieee_mode_off() #2 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -143,10 +143,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_ps void @ps_ieee_mode_default() #0 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -158,10 +158,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_ps void @ps_ieee_mode_on() #1 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }
 
@@ -173,10 +173,10 @@
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
 ; GCN-NOT: v_mul_f32
 define amdgpu_ps void @ps_ieee_mode_off() #2 {
-  %val0 = load volatile float, float addrspace(1)* undef
-  %val1 = load volatile float, float addrspace(1)* undef
+  %val0 = load volatile float, ptr addrspace(1) undef
+  %val1 = load volatile float, ptr addrspace(1) undef
   %min = call float @llvm.minnum.f32(float %val0, float %val1)
-  store volatile float %min, float addrspace(1)* undef
+  store volatile float %min, ptr addrspace(1) undef
   ret void
 }