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annotate llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents 79ff65ed7e25
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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173
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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1 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2
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3 ; GCN-LABEL: {{^}}kernel_ieee_mode_default:
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4 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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5 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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6 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
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7 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
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8 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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9 ; GCN-NOT: v_mul_f32
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10 define amdgpu_kernel void @kernel_ieee_mode_default() #0 {
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1f2b6ac9f198 LLVM16-1
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parents: 221
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11 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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parents: 221
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12 %val1 = load volatile float, ptr addrspace(1) undef
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13 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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1f2b6ac9f198 LLVM16-1
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parents: 221
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14 store volatile float %min, ptr addrspace(1) undef
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15 ret void
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16 }
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17
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18 ; GCN-LABEL: {{^}}kernel_ieee_mode_on:
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19 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
diff changeset
20 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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21 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
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22 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
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23 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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24 ; GCN-NOT: v_mul_f32
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25 define amdgpu_kernel void @kernel_ieee_mode_on() #1 {
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1f2b6ac9f198 LLVM16-1
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parents: 221
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26 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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parents: 221
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27 %val1 = load volatile float, ptr addrspace(1) undef
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28 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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1f2b6ac9f198 LLVM16-1
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parents: 221
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29 store volatile float %min, ptr addrspace(1) undef
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30 ret void
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31 }
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32
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33 ; GCN-LABEL: {{^}}kernel_ieee_mode_off:
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34 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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35 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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36 ; GCN-NOT: [[VAL0]]
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37 ; GCN-NOT: [[VAL1]]
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38 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
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39 ; GCN-NOT: v_mul_f32
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40 define amdgpu_kernel void @kernel_ieee_mode_off() #2 {
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1f2b6ac9f198 LLVM16-1
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parents: 221
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41 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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parents: 221
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42 %val1 = load volatile float, ptr addrspace(1) undef
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43 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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parents: 221
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44 store volatile float %min, ptr addrspace(1) undef
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45 ret void
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46 }
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47
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48 ; GCN-LABEL: {{^}}func_ieee_mode_default:
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49 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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50 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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51 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
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52 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
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53 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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54 ; GCN-NOT: v_mul_f32
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55 define void @func_ieee_mode_default() #0 {
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1f2b6ac9f198 LLVM16-1
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parents: 221
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56 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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parents: 221
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57 %val1 = load volatile float, ptr addrspace(1) undef
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58 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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1f2b6ac9f198 LLVM16-1
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parents: 221
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59 store volatile float %min, ptr addrspace(1) undef
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60 ret void
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61 }
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62
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63 ; GCN-LABEL: {{^}}func_ieee_mode_on:
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64 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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65 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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66 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
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67 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
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68 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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69 ; GCN-NOT: v_mul_f32
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70 define void @func_ieee_mode_on() #1 {
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1f2b6ac9f198 LLVM16-1
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parents: 221
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71 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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parents: 221
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72 %val1 = load volatile float, ptr addrspace(1) undef
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73 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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1f2b6ac9f198 LLVM16-1
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parents: 221
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74 store volatile float %min, ptr addrspace(1) undef
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75 ret void
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76 }
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77
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78 ; GCN-LABEL: {{^}}func_ieee_mode_off:
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79 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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80 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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81 ; GCN-NOT: [[VAL0]]
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82 ; GCN-NOT: [[VAL1]]
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83 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
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84 ; GCN-NOT: v_mul_f32
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85 define void @func_ieee_mode_off() #2 {
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86 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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parents: 221
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87 %val1 = load volatile float, ptr addrspace(1) undef
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88 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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1f2b6ac9f198 LLVM16-1
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parents: 221
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89 store volatile float %min, ptr addrspace(1) undef
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90 ret void
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91 }
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92
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93 ; GCN-LABEL: {{^}}cs_ieee_mode_default:
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94 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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95 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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96 ; GCN-NOT: [[VAL0]]
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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97 ; GCN-NOT: [[VAL1]]
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98 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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99 ; GCN-NOT: v_mul_f32
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100 define amdgpu_cs void @cs_ieee_mode_default() #0 {
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101 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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102 %val1 = load volatile float, ptr addrspace(1) undef
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103 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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parents: 221
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104 store volatile float %min, ptr addrspace(1) undef
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105 ret void
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106 }
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107
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108 ; GCN-LABEL: {{^}}cs_ieee_mode_on:
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109 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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110 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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111 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
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112 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
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113 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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114 ; GCN-NOT: v_mul_f32
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115 define amdgpu_cs void @cs_ieee_mode_on() #1 {
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116 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
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117 %val1 = load volatile float, ptr addrspace(1) undef
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118 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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119 store volatile float %min, ptr addrspace(1) undef
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120 ret void
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121 }
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122
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123 ; GCN-LABEL: {{^}}cs_ieee_mode_off:
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124 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
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parents: 173
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125 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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126 ; GCN-NOT: [[VAL0]]
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127 ; GCN-NOT: [[VAL1]]
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128 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
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129 ; GCN-NOT: v_mul_f32
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130 define amdgpu_cs void @cs_ieee_mode_off() #2 {
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131 %val0 = load volatile float, ptr addrspace(1) undef
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132 %val1 = load volatile float, ptr addrspace(1) undef
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133 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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1f2b6ac9f198 LLVM16-1
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134 store volatile float %min, ptr addrspace(1) undef
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135 ret void
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136 }
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137
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138 ; GCN-LABEL: {{^}}ps_ieee_mode_default:
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139 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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140 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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141 ; GCN-NOT: [[VAL0]]
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142 ; GCN-NOT: [[VAL1]]
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143 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
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144 ; GCN-NOT: v_mul_f32
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145 define amdgpu_ps void @ps_ieee_mode_default() #0 {
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146 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 221
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147 %val1 = load volatile float, ptr addrspace(1) undef
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148 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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149 store volatile float %min, ptr addrspace(1) undef
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150 ret void
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151 }
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152
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153 ; GCN-LABEL: {{^}}ps_ieee_mode_on:
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154 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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155 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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156 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
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157 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
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158 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
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159 ; GCN-NOT: v_mul_f32
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160 define amdgpu_ps void @ps_ieee_mode_on() #1 {
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161 %val0 = load volatile float, ptr addrspace(1) undef
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parents: 221
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162 %val1 = load volatile float, ptr addrspace(1) undef
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163 %min = call float @llvm.minnum.f32(float %val0, float %val1)
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parents: 221
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164 store volatile float %min, ptr addrspace(1) undef
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165 ret void
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166 }
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167
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168 ; GCN-LABEL: {{^}}ps_ieee_mode_off:
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169 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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170 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
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171 ; GCN-NOT: [[VAL0]]
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172 ; GCN-NOT: [[VAL1]]
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173 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
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174 ; GCN-NOT: v_mul_f32
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175 define amdgpu_ps void @ps_ieee_mode_off() #2 {
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1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 221
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176 %val0 = load volatile float, ptr addrspace(1) undef
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 221
diff changeset
177 %val1 = load volatile float, ptr addrspace(1) undef
150
anatofuz
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178 %min = call float @llvm.minnum.f32(float %val0, float %val1)
252
1f2b6ac9f198 LLVM16-1
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 221
diff changeset
179 store volatile float %min, ptr addrspace(1) undef
150
anatofuz
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180 ret void
anatofuz
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181 }
anatofuz
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182
anatofuz
parents:
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183 declare float @llvm.minnum.f32(float, float) #3
anatofuz
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184
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185 attributes #0 = { nounwind }
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186 attributes #1 = { nounwind "amdgpu-ieee"="true" }
anatofuz
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187 attributes #2 = { nounwind "amdgpu-ieee"="false" }
anatofuz
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188 attributes #3 = { nounwind readnone speculatable }