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diff test/CodeGen/Mips/llvm-ir/srem.ll @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 1172e4bd9c6f
children c2174574ed3a
line wrap: on
line diff
--- a/test/CodeGen/Mips/llvm-ir/srem.ll	Fri Feb 16 19:10:49 2018 +0900
+++ b/test/CodeGen/Mips/llvm-ir/srem.ll	Sat Feb 17 09:57:20 2018 +0900
@@ -30,8 +30,6 @@
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -166,9 +164,6 @@
 
   ; MM32:         lw      $25, %call16(__moddi3)($2)
 
-  ; MM64:         dmod    $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = srem i64 %a, %b
   ret i64 %r
 }
@@ -184,8 +179,6 @@
 
   ; MM32:         lw      $25, %call16(__modti3)($16)
 
-  ; MM64:         ld      $25, %call16(__modti3)($2)
-
   %r = srem i128 %a, %b
   ret i128 %r
 }