Mercurial > hg > CbC > CbC_llvm
diff test/CodeGen/Thumb/tbb-reuse.mir @ 134:3a76565eade5 LLVM5.0.1
update 5.0.1
| author | mir3636 |
|---|---|
| date | Sat, 17 Feb 2018 09:57:20 +0900 |
| parents | 803732b1fca8 |
| children |
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--- a/test/CodeGen/Thumb/tbb-reuse.mir Fri Feb 16 19:10:49 2018 +0900 +++ b/test/CodeGen/Thumb/tbb-reuse.mir Sat Feb 17 09:57:20 2018 +0900 @@ -63,21 +63,21 @@ selected: false tracksRegLiveness: true liveins: - - { reg: '%r0' } -calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', - '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', - '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', - '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', - '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', - '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', - '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', - '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', - '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', - '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', - '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', - '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', - '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', - '%d11_d12_d13_d14' ] + - { reg: '$r0' } +calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13', + '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4', + '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11', + '$s16', '$s17', '$s18', '$s19', '$s20', '$s21', + '$s22', '$s23', '$s24', '$s25', '$s26', '$s27', + '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11', + '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15', + '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5', + '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11', + '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14', + '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14', + '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15', + '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12', + '$d11_d12_d13_d14' ] frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -93,8 +93,8 @@ hasVAStart: false hasMustTailInVarArgFunc: false stack: - - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false } - - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false } + - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' } jumpTable: kind: inline entries: @@ -106,46 +106,46 @@ body: | bb.0.entry: successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668) - liveins: %r0, %r7, %lr + liveins: $r0, $r7, $lr - frame-setup tPUSH 14, _, killed %r7, killed %lr, implicit-def %sp, implicit %sp + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 - frame-setup CFI_INSTRUCTION offset %lr, -4 - frame-setup CFI_INSTRUCTION offset %r7, -8 - %r1, dead %cpsr = tSUBi3 %r0, 1, 14, _ - tCMPi8 %r1, 3, 14, _, implicit-def %cpsr - tBcc %bb.2.default, 8, killed %cpsr + frame-setup CFI_INSTRUCTION offset $lr, -4 + frame-setup CFI_INSTRUCTION offset $r7, -8 + $r1, dead $cpsr = tSUBi3 $r0, 1, 14, $noreg + tCMPi8 $r1, 3, 14, $noreg, implicit-def $cpsr + tBcc %bb.2.default, 8, killed $cpsr bb.1.entry: successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000) - liveins: %r0, %r1 + liveins: $r0, $r1 - %r1, dead %cpsr = tLSLri killed %r1, 2, 14, _ - %r2 = tLEApcrelJT %jump-table.0, 14, _ - %r2 = tLDRr killed %r1, killed %r2, 14, _ :: (load 4 from jump-table) - %r1, dead %cpsr = tLSLri %r2, 2, 14, _ - tBR_JTr killed %r2, %jump-table.0 + $r1, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg + $r2 = tLEApcrelJT %jump-table.0, 14, $noreg + $r2 = tLDRr killed $r1, killed $r2, 14, $noreg :: (load 4 from jump-table) + $r1, dead $cpsr = tLSLri $r2, 2, 14, $noreg + tBR_JTr killed $r2, %jump-table.0 bb.2.default: - tBL 14, _, @exit0, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp - tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp + tBL 14, $noreg, @exit0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp bb.3.lab1: - liveins: %r0,%r1 + liveins: $r0,$r1 - tBL 14, _, @exit1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp - tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp + tBL 14, $noreg, @exit1, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp + tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp bb.4.lab2: - tBL 14, _, @exit2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp - tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp + tBL 14, $noreg, @exit2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp bb.5.lab3: - tBL 14, _, @exit3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp - tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp + tBL 14, $noreg, @exit3, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp bb.6.lab4: - tBL 14, _, @exit4, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp - tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp + tBL 14, $noreg, @exit4, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp ...