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121
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1 # RUN: llc -run-pass arm-cp-islands %s -o - | FileCheck %s
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2
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3 --- |
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4 ; ModuleID = '<stdin>'
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5 source_filename = "<stdin>"
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6 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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7 target triple = "thumbv6m--none-eabi"
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8
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9 declare void @exit0()
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10
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11 declare void @exit1(i32)
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12
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13 declare void @exit2()
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14
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15 declare void @exit3()
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16
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17 declare void @exit4()
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18
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19 define void @jump_table(i32 %val, i32 %arg2, i32 %arg3, i32 %arg4) {
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20 entry:
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21 switch i32 %val, label %default [
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22 i32 1, label %lab1
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23 i32 2, label %lab2
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24 i32 3, label %lab3
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25 i32 4, label %lab4
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26 ]
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27
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28 default: ; preds = %entry
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29 tail call void @exit0()
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30 ret void
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31
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32 lab1: ; preds = %entry
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33 %b = sub i32 %val, 1
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34 %a = shl i32 %b, 2
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35 tail call void @exit1(i32 %a)
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36 ret void
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37
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38 lab2: ; preds = %entry
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39 tail call void @exit2()
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40 ret void
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41
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42 lab3: ; preds = %entry
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43 tail call void @exit3()
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44 ret void
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45
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46 lab4: ; preds = %entry
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47 tail call void @exit4()
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48 ret void
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49 }
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50
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51 ; Function Attrs: nounwind
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52 declare void @llvm.stackprotector(i8*, i8**) #0
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53
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54 attributes #0 = { nounwind }
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55
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56 ...
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57 ---
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58 name: jump_table
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59 alignment: 1
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60 exposesReturnsTwice: false
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61 legalized: false
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62 regBankSelected: false
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63 selected: false
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64 tracksRegLiveness: true
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65 liveins:
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134
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66 - { reg: '$r0' }
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67 calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
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68 '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
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69 '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
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70 '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
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71 '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
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72 '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
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73 '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
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74 '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
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75 '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
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76 '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
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77 '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
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78 '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
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79 '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
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80 '$d11_d12_d13_d14' ]
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121
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81 frameInfo:
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82 isFrameAddressTaken: false
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83 isReturnAddressTaken: false
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84 hasStackMap: false
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85 hasPatchPoint: false
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86 stackSize: 8
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87 offsetAdjustment: 0
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88 maxAlignment: 4
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89 adjustsStack: true
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90 hasCalls: true
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91 maxCallFrameSize: 0
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92 hasOpaqueSPAdjustment: false
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93 hasVAStart: false
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94 hasMustTailInVarArgFunc: false
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95 stack:
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134
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96 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
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97 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
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121
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98 jumpTable:
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99 kind: inline
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100 entries:
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101 - id: 0
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102 blocks: [ '%bb.3.lab1', '%bb.4.lab2', '%bb.5.lab3', '%bb.6.lab4' ]
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103 # r1 is redefined in the middle of the recognizable jump sequence - it shouldn't be clobbered!
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104 # CHECK-NOT: tTBB_JT
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105
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106 body: |
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107 bb.0.entry:
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108 successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668)
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134
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109 liveins: $r0, $r7, $lr
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121
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110
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134
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111 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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121
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112 frame-setup CFI_INSTRUCTION def_cfa_offset 8
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134
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113 frame-setup CFI_INSTRUCTION offset $lr, -4
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114 frame-setup CFI_INSTRUCTION offset $r7, -8
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115 $r1, dead $cpsr = tSUBi3 $r0, 1, 14, $noreg
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116 tCMPi8 $r1, 3, 14, $noreg, implicit-def $cpsr
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117 tBcc %bb.2.default, 8, killed $cpsr
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121
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118
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119 bb.1.entry:
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120 successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000)
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134
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121 liveins: $r0, $r1
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121
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122
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134
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123 $r1, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
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124 $r2 = tLEApcrelJT %jump-table.0, 14, $noreg
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125 $r2 = tLDRr killed $r1, killed $r2, 14, $noreg :: (load 4 from jump-table)
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126 $r1, dead $cpsr = tLSLri $r2, 2, 14, $noreg
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127 tBR_JTr killed $r2, %jump-table.0
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121
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128
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129 bb.2.default:
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134
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130 tBL 14, $noreg, @exit0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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131 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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121
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132
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133 bb.3.lab1:
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134
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134 liveins: $r0,$r1
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121
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135
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134
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136 tBL 14, $noreg, @exit1, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp
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137 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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121
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138
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139 bb.4.lab2:
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134
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140 tBL 14, $noreg, @exit2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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141 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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121
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142
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143 bb.5.lab3:
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134
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144 tBL 14, $noreg, @exit3, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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145 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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121
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146
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147 bb.6.lab4:
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134
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148 tBL 14, $noreg, @exit4, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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149 tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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121
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150
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151 ...
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