--- a/test/CodeGen/AMDGPU/setcc.ll	Tue Oct 13 17:49:56 2015 +0900
+++ b/test/CodeGen/AMDGPU/setcc.ll	Tue Jan 26 22:53:40 2016 +0900
@@ -375,3 +375,37 @@
   store <3 x i8> %ext, <3 x i8> addrspace(1)* %gep.out
   ret void
 }
+
+; Make sure we don't try to emit i1 setcc ops
+; FUNC-LABEL: setcc-i1
+; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 1
+; SI: v_cmp_eq_i32_e64 s[0:1], 0, [[AND]]
+define void @setcc-i1(i32 %in) {
+  %and = and i32 %in, 1
+  %cmp = icmp eq i32 %and, 0
+  br i1 %cmp, label %endif, label %if
+if:
+  unreachable
+endif:
+  ret void
+}
+
+; FUNC-LABEL: setcc-i1-and-xor
+; SI-DAG: v_cmp_le_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
+; SI-DAG: v_cmp_ge_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], 1.0, s{{[0-9]+}}
+; SI: s_and_b64 s[2:3], [[A]], [[B]]
+define void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 {
+bb0:
+  %tmp5 = fcmp oge float %cond, 0.000000e+00
+  %tmp7 = fcmp ole float %cond, 1.000000e+00
+  %tmp9 = and i1 %tmp5, %tmp7
+  %tmp11 = xor i1 %tmp9, 1
+  br i1 %tmp11, label %bb2, label %bb1
+
+bb1:
+  store i32 0, i32 addrspace(1)* %out
+  br label %bb2
+
+bb2:
+  ret void
+}