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view test/CodeGen/X86/legalize-shl-vec.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
line wrap: on
line source

; RUN: llc < %s -march=x86-64 | FileCheck %s

define <2 x i256> @test_shl(<2 x i256> %In) {
  %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
  %Out = shl <2 x i256> %In, %Amt
  ret <2 x i256> %Out

  ; CHECK-LABEL: test_shl
  ; CHECK:       movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK:       retq
}

define <2 x i256> @test_srl(<2 x i256> %In) {
  %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
  %Out = lshr <2 x i256> %In, %Amt
  ret <2 x i256> %Out

  ; CHECK-LABEL: test_srl
  ; CHECK:       movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK-NEXT:  movq $0
  ; CHECK:       retq
}

define <2 x i256> @test_sra(<2 x i256> %In) {
  %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
  %Out = ashr <2 x i256> %In, %Amt
  ret <2 x i256> %Out

  ; CHECK-LABEL: test_sra
  ; CHECK:       sarq $63
}