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changeset 247:6c632a06ee27

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 16 Aug 2023 17:50:41 +0900
parents 7a500f3ef647
children cfe92afade2b
files llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.td
diffstat 3 files changed, 37 insertions(+), 77 deletions(-) [+]
line wrap: on
line diff
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp	Sun Aug 13 19:54:59 2023 +0900
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp	Wed Aug 16 17:50:41 2023 +0900
@@ -1539,76 +1539,6 @@
   case TargetOpcode::FAULTING_OP:
     return LowerFAULTING_OP(*MI);
 
-  case AArch64::t2Int_eh_sjlj_setjmp:
-  case AArch64::t2Int_eh_sjlj_setjmp_nofp:
-  case AArch64::tInt_eh_sjlj_setjmp: {
-    // Two incoming args: GPR:$src, GPR:$val
-    // mov $val, pc
-    // adds $val, #7
-    // str $val, [$src, #4]
-    // movs r0, #0
-    // b LSJLJEH
-    // movs r0, #1
-    // LSJLJEH:
-    Register SrcReg = MI->getOperand(0).getReg();
-    Register ValReg = MI->getOperand(1).getReg();
-    MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
-    OutStreamer->AddComment("eh_setjmp begin");
-    EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::tMOVr)
-      .addReg(ValReg)
-      .addReg(AArch64::PC)
-      // Predicate.
-      .addImm(AArch64CC::AL)
-      .addReg(0));
-
-    EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::tADDi3)
-      .addReg(ValReg)
-      // 's' bit operand
-      .addReg(AArch64::CPSR)
-      .addReg(ValReg)
-      .addImm(7)
-      // Predicate.
-      .addImm(AArch64CC::AL)
-      .addReg(0));
-
-    EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::tSTRi)
-      .addReg(ValReg)
-      .addReg(SrcReg)
-      // The offset immediate is #4. The operand value is scaled by 4 for the
-      // tSTR instruction.
-      .addImm(1)
-      // Predicate.
-      .addImm(AArch64CC::AL)
-      .addReg(0));
-
-    EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::tMOVi8)
-      .addReg(AArch64::R0)
-      .addReg(AArch64::CPSR)
-      .addImm(0)
-      // Predicate.
-      .addImm(AArch64CC::AL)
-      .addReg(0));
-
-    const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
-    EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::tB)
-      .addExpr(SymbolExpr)
-      .addImm(AArch64CC::AL)
-      .addReg(0));
-
-    OutStreamer->AddComment("eh_setjmp end");
-    EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::tMOVi8)
-      .addReg(AArch64::R0)
-      .addReg(AArch64::CPSR)
-      .addImm(1)
-      // Predicate.
-      .addImm(AArch64CC::AL)
-      .addReg(0));
-
-    OutStreamer->emitLabel(Label);
-    return;
-  }
-
-  case AArch64::Int_eh_sjlj_setjmp_nofp:
   case AArch64::Int_eh_sjlj_setjmp: {
     // Two incoming args: GPR:$src, GPR:$val
     // add $val, pc, #8
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp	Sun Aug 13 19:54:59 2023 +0900
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp	Wed Aug 16 17:50:41 2023 +0900
@@ -562,8 +562,8 @@
   setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
   setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
-  if (Subtarget->useSjLjEH())
-    setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
+  // if (Subtarget->useSjLjEH())
+  //  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
 
   // Custom lower Add/Sub/Mul with overflow.
   setOperationAction(ISD::SADDO, MVT::i32, Custom);
@@ -2726,13 +2726,8 @@
     return EmitAddVectorToTile(AArch64::ADDVA_MPPZ_D, AArch64::ZAD0, MI, BB);
 
   case AArch64::Int_eh_sjlj_setjmp:
-  case AArch64::Int_eh_sjlj_setjmp_nofp:
     return BB;
 
-  case AArch64::Int_eh_sjlj_setup_dispatch:
-    EmitSjLjDispatchBlock(MI, BB);
-    return BB;
-  }
 }
 
 //===----------------------------------------------------------------------===//
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td	Sun Aug 13 19:54:59 2023 +0900
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td	Wed Aug 16 17:50:41 2023 +0900
@@ -355,6 +355,11 @@
   SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
 ]>;
 
+def SDT_AArch64EH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
+                                                 SDTCisInt<2>]>;           
+def SDT_AArch64EH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
+def SDT_AArch64EH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
+
 // non-extending masked load fragment.
 def nonext_masked_load :
   PatFrag<(ops node:$ptr, node:$pred, node:$def),
@@ -2543,6 +2548,36 @@
 defm TBZ  : TestBranch<0, "tbz", AArch64tbz>;
 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
 
+      
+let Defs =                                                            
+  [ X0,  LR ], 
+  hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1, Size = 20 in {
+  def Int_eh_sjlj_setjmp : Pseudo<(outs), (ins GPR64:$src, GPR64:$val),
+                         [(set X0, (AArch64eh_sjlj_setjmp GPR64:$src, GPR64:$val))]>,
+                      Sched<[WriteBrReg]>,
+                           Requires<[]>;                    
+}                                                                             
+                                                                        
+// This gets lowered to an instruction sequence of 20 bytes      
+//let Defs =                                                       
+//  [ X0,  LR ],
+//  hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1, Size = 20 in {
+//  def Int_eh_sjlj_setjmp_nofp : Pseudo<(outs), (ins GPR64:$src, GPR64:$val),
+//                         [(set X0, (AArch64eh_sjlj_setjmp GPR64:$src, GPR64:$val))]>,
+//                      Sched<[WriteBrReg]>,
+//                                Requires<[]>;
+//}
+
+// This gets lowered to an instruction sequence of 16 bytes
+// FIXME: Non-IOS version(s)
+let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, Size = 16,
+    Defs = [ X7, LR, SP ] in {
+def Int_eh_sjlj_longjmp : Pseudo<(outs), (ins GPR64:$src, GPR64:$scratch),
+                         [(AArch64eh_sjlj_longjmp GPR64:$src, GPR64:$scratch)]>,
+                      Sched<[WriteBrReg]>,
+                                Requires<[]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Unconditional branch (immediate) instructions.
 //===----------------------------------------------------------------------===//