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annotate level1/modules/boot_1773.asm @ 1893:1827bb446188

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Modified booters to use new boot strategy with boot_common.asm
author boisy
date Sat, 15 Oct 2005 15:32:45 +0000
parents 5f8822fb42e0
children 6d5bd8549d28
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1 ********************************************************************
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2 * Boot - WD1773 Boot module
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3 *
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4 * $Id$
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5 *
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6 * Edt/Rev YYYY/MM/DD Modified by
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7 * Comment
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8 * ------------------------------------------------------------------
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9 * 4 1985/??/??
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10 * Original Tandy distribution version.
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11 *
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12 * 6 1998/10/12 Boisy G. Pitre
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13 * Obtained from L2 Upgrade archive, has 6ms step rate and disk timeout
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14 * changes.
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15 *
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16 * 6r2 2003/05/18 Boisy G. Pitre
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17 * Added '.' output for each sector for OS-9 L2 and NitrOS9 for
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18 * Mark Marlette (a special request :).
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19 *
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20 * 6r3 2003/08/31 Robert Gault
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21 * Put BLOB-stop code in place, changed orb #$30 to orb #$28
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22 *
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23 * 6r4 2004/02/17 Rodney Hamilton
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24 * Minor optimizations, improvements in source comments
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25 *
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26 * 7 2005/10/10 Boisy G. Pitre
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27 * Added fragmented bootfile support
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28 * 7 2005/10/13 Robert Gault
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29 * Changed timing loops for H6309L2 so that code shortened enough to
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30 * fit within the $1D0 boundary.
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31
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32 nam Boot
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33 ttl WD1773 Boot module
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34
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35 IFP1
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36 use defsfile
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37 ENDC
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38
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39 * FDC Control Register bits at $FF40
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40 HALTENA equ %10000000
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41 SIDESEL equ %01000000 DRVSEL3 if no DS drives
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42 DDEN equ %00100000
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43 READY equ %00010000 READY for Tandy WD1773-based controllers
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44 MOTON equ %00001000
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45 DRVSEL2 equ %00000100
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46 DRVSEL1 equ %00000010
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47 DRVSEL0 equ %00000001
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48
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49 * Default Boot is from drive 0
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50 BootDr set DRVSEL0
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51 IFEQ DNum-1
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52 BootDr set DRVSEL1 Alternate boot from drive 1
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53 ENDC
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54 IFEQ DNum-2
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55 BootDr set DRVSEL2 Alternate boot from drive 2
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56 ENDC
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57 IFEQ DNum-3
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58 BootDr set SIDESEL Alternate boot from drive 3
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59 ENDC
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60
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61 * WD17x3 DPort offsets
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62 CONTROL equ 0
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63 CMDREG equ 8+0 write-only
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64 STATREG equ CMDREG read-only
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65 TRACKREG equ 8+1
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66 SECTREG equ 8+2
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67 DATAREG equ 8+3
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68
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69 * Sector Size
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70 SECTSIZE equ 256
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71
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72 * Step Rates:
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73 * $00 = 6ms
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74 * $01 = 12ms
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75 * $02 = 20ms
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76 * $03 = 30ms
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77 STEP set $00
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78
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79 tylg set Systm+Objct
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80 atrv set ReEnt+rev
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81 rev set $00
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82 edition set 7
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83
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84 mod eom,name,tylg,atrv,start,size
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85
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86 * NOTE: these are U-stack offsets, not DP
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87 seglist rmb 2 pointer to segment list
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88 blockloc rmb 2 pointer to memory requested
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89 blockimg rmb 2 duplicate of the above
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90 bootloc rmb 3 sector pointer; not byte pointer
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91 bootsize rmb 2 size in bytes
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92 drvsel rmb 1
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93 currtrak rmb 1
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94 ddtks rmb 1 no. of sectors per track
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95 ddfmt rmb 1
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96 side rmb 1 side 2 flag
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97 size equ .
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98
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99 name fcs /Boot/
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100 fcb edition
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101
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102 FLOPPY equ 1
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103
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104 ************ START OF DEVICE-SPECIFIC INIT ***********
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105 * HWInit - Initialize the device
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106 HWInit
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107 ldy Address,pcr get hardware address
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108 lda #%11010000 ($D0) Force Interrupt (stops any command in progress)
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109 sta CMDREG,y write command to command register
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110 lbsr Delay2 delay 54~
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111 lda STATREG,y clear status register
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112 lda #$FF
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113 sta currtrak,u set current track to 255
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114 leax >NMIRtn,pcr point to NMI routine
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115 IFGT Level-1
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116 stx <D.NMI save address
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117 ELSE
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118 stx >D.XNMI+1 save address
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119 lda #$7E
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120 sta >D.XNMI
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121 ENDC
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122 lda #MOTON turn on drive motor
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123 ora WhichDrv,pcr
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124 sta CONTROL,y
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125 * MOTOR ON spin-up delay loop (~307 mSec)
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126 IFGT Level-1
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127 IFNE H6309
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128 ldd #$F000 3 cycles
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129 ELSE
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130 ldd #50000
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131 ENDC
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132 ELSE
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133 ldd #25000
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134 ENDC
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135 * IFNE H6309
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136 * nop
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137 * ENDC
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138 L003A nop 1 cycles
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139 nop 1 cycles
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140 * IFNE H6309
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141 * nop
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142 * nop
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143 * nop
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144 * ENDC
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145 subd #$0001 4 cycles
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146 bne L003A 3 cycles
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147 HWTerm rts
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148 ************ END OF DEVICE-SPECIFIC INIT ***********
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149
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150 use ../../6809l1/modules/boot_common.asm
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151
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152 ************************************************************
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153 ************************************************************
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154 * Hardware-Specific Booter Area *
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155 ************************************************************
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156 ************************************************************
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157
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158
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159 DoDDns lda #DDEN+MOTON double density enable and motor on
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160 ora WhichDrv,pcr OR in selected drive
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161 sta drvsel,u save drive selection byte
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162 clr currtrak,u clear current track
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163 lda #$05
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164 lbsr SetTrak Set the track to the head we want
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165 ldb #0+STEP RESTORE cmd
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166 lbra Talk2FDC send command and wait for it to complete
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167
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168 *
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169 * HWRead - Read a 256 byte sector from the device
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170 * Entry: Y = hardware address
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171 * B = bits 23-16 of LSN
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172 * X = bits 15-0 of LSN
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173 * blockloc,u = ptr to 256 byte sector
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174 * Exit: X = ptr to data (i.e. ptr in blockloc,u)
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175 *
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176 * Read a sector from the 1773
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177 * Entry: B,X = LSN to read
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178 HWRead lda #$91
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179 bsr L00DF else branch subroutine
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180 bcs HWRRts branch if error
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181 ldx blockloc,u get buffer pointer in X for caller
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182 clrb
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183 HWRRts rts
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184
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185 L00D7 bcc L00DF
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186 pshs x,b,a
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187 bsr DoDDns
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188 puls x,b,a
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189 L00DF pshs x,b,a save LSN, command
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190 bsr ReadSect
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191 puls x,b,a restore LSN, command
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192 bcc HWRRts branch if OK
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193 lsra
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194 bne L00D7
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195 ReadSect bsr Seek2Sect seek to the sector stored in X
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196 bcs HWRRts if error, return to caller
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197 ldx blockloc,u get address of buffer to fill
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198 orcc #IntMasks mask interrupts
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199 pshs x save X
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200 ldx #$FFFF
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201 ldb #%10000000 ($80) READ SECTOR command
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202 stb CMDREG,y write to command register
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203 ldb drvsel,u (DDEN+MOTORON+BootDr)
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204 * NOTE: The 1773 FDC multiplexes the write precomp enable and ready
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205 * signals on the ENP/RDY pin, so the READY bit must always be ON for
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206 * read and seek commands. (from the FD502 FDC Service Manual)
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207 orb #DDEN+READY set DDEN+READY bits ($30)
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208 tst side,u are we on side 2?
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209 beq L0107
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210 orb #SIDESEL set side 2 bit
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211 L0107 stb CONTROL,y
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212 lbsr Delay2 delay 54~
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213 orb #HALTENA HALT enable ($80)
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214 * lda #%00000010 RESTORE cmd ($02)
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215 *L0111 bita >DPort+STATREG
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216 * bne L0123
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217 * leay -$01,y
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218 * bne L0111
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219 * lda drvsel,u
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220 * sta >DPort+CONTROL
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221 * puls y
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222 * bra L0138
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223 stb CONTROL,y
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224 nop
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225 nop
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226 * bra L0123
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227
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228 ldx ,s get X saved earlier
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229 * Sector READ Loop
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230 L0123 lda DATAREG,y read from WD DATA register
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231 sta ,x+
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232 * stb >DPort+CONTROL
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233 nop
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234 bra L0123
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235 * RVH NOTE: This ONLY works for double density boot disks! The Tandy
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236 * controllers internally gate HALT enable with the DDEN bit, which
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237 * means that reading a single-density boot disk will not generate the
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238 * NMI signal needed to exit the read loop! Single-density disks must
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239 * use a polled I/O loop instead.
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240 NMIRtn leas R$Size,s adjust stack
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241 puls x
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242 ldb STATREG,y read WD STATUS register
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243 bitb #$9C any errors?
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244 * bitb #$04 LOST DATA bit set?
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245 beq r@ branch if not
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246 * beq ChkErr branch if not
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247 L0138 comb else we will return error
210
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248 ldb #E$Read
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249 r@ rts
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250
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251 Seek2Sect
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252 lda #MOTON permit alternate drives
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253 ora WhichDrv,pcr permit alternate drives
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254 sta drvsel,u save byte to static mem
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255 clr side,u start on side 1
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256 tfr x,d move LSN into D
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257 cmpd #$0000 zero?
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258 beq L016C branch if so
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259 clr ,-s else clear space on stack
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260 tst ddfmt,u double sided disk?
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261 beq SnglSid branch if not
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262 bra DblSid
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263 * Double-sided code
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264 L0152 com side,u flag side 2
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265 bne DblSid
210
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266 inc ,s
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267 DblSid subb ddtks,u
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268 sbca #$00
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269 bcc L0152
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270 bra L0168
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271 L0160 inc ,s
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272 SnglSid subb ddtks,u subtract sectors per track from B
210
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273 sbca #$00
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274 bcc L0160
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275 L0168 addb #18 add sectors per track (should this be ddtks?)
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276 puls a get current track indicator off of stack
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277 L016C incb
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278 stb SECTREG,y save in sector register
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279 SetTrak ldb currtrak,u get current track in B
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280 stb TRACKREG,y save in track register
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281 cmpa currtrak,u same as A?
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282 beq rtsok branch if so
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283 sta currtrak,u
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284 sta DATAREG,y
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285 ldb #$10+STEP SEEK command
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286 bsr Talk2FDC send command to controller
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287 pshs x
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288 * Seek Delay
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289 ldx #$222E delay ~39 mSec (78mS L1)
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290 SeekDly leax -$01,x
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291 bne SeekDly
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292 puls x
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293 rtsok clrb
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294 rts
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295
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296 *ChkErr bitb #$98 evaluate WD status (READY, RNF, CRC err)
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297 * bne L0138
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298 * clrb
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299 * rts
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300
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301 Talk2FDC bsr DoCMD issue FDC cmd, wait 54~
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302 FDCLoop ldb STATREG,y get status
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303 bitb #$01 still BUSY?
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304 bne FDCLoop loop until command completes
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305 rts
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306
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307 * Issue command and wait 54 clocks
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308 * Controller requires a min delay of 14uS (DD) or 28uS (SD)
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309 * following a command write before status register is valid
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310 DoCMD bsr SelNSend
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311 * Delay branches
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312 * 54 clock delay including bsr (=30uS/L2,60us/L1)
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313 * H6309 code changed to reduce code size, RG
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314 IFEQ H6309
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315 Delay2
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316 lbsr Delay3
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317 Delay3
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318 lbsr Delay4
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319 Delay4
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diff changeset
320 ELSE
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321 Delay2 lda #5 3 cycles
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322 Delay3 exg a,a 5 cycles | 10*5
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323 deca 2 cycles |
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diff changeset
324 bne Delay3 3 cycles |
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325 ENDC
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326 rts
210
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327
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328 * Select And Send
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329 * Entry: B = command byte
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330 SelNSend lda drvsel,u
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331 sta CONTROL,y
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332 stb CMDREG,y
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333 rts
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334
1166
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diff changeset
335 IFGT Level-1
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336 * Filler to get $1D0
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337 Filler fill $39,$1D0-3-2-1-*
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diff changeset
338 ENDC
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339
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340 Address fdb DPort
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341 WhichDrv fcb BootDr
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342
0
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343 emod
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344 eom equ *
48
cdfe69117a2f Cleaned up source
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345 end