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annotate level1/modules/boot_1773.asm @ 3169:1ff3d7673e36

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mc09 l2: bring sys/makefile in line with latest organisation for other platforms Revise bootfiles/makefile to remove sysgo from bootfile - it can be found on the root of the disk.
author Neal Crook <foofoobedoo@gmail.com>
date Mon, 17 Apr 2017 22:59:28 +0100
parents e0614e08fa5e
children
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1 ********************************************************************
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2 * Boot - WD1773 Boot module
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3 * Provides HWInit, HWTerm, HWRead which are called by code in
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4 * "use"d boot_common.asm
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5 *
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6 * $Id$
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7 *
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8 * Edt/Rev YYYY/MM/DD Modified by
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9 * Comment
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10 * ------------------------------------------------------------------
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11 * 4 1985/??/??
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12 * Original Tandy distribution version.
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13 *
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14 * 6 1998/10/12 Boisy G. Pitre
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15 * Obtained from L2 Upgrade archive, has 6ms step rate and disk timeout
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16 * changes.
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17 *
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18 * 6r2 2003/05/18 Boisy G. Pitre
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19 * Added '.' output for each sector for OS-9 L2 and NitrOS9 for
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20 * Mark Marlette (a special request :).
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21 *
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22 * 6r3 2003/08/31 Robert Gault
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23 * Put BLOB-stop code in place, changed orb #$30 to orb #$28
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24 *
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25 * 6r4 2004/02/17 Rodney Hamilton
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26 * Minor optimizations, improvements in source comments
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27 *
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28 * 7 2005/10/10 Boisy G. Pitre
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29 * Added fragmented bootfile support
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30 *
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31 * 7 2005/10/13 Robert Gault
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32 * Changed timing loops for H6309L2 so that code shortened enough to
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33 * fit within the $1D0 boundary.
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34 *
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35 * 8 2006/03/03 Boisy G. Pitre
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36 * Drive motors now turned off before returning to kernel.
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37 *
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38 * 9 2006/05/05 Boisy G. Pitre
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39 * Fixed bug where single sided booting was broken
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40 *
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41 * 2006/06/04 Boisy G. Pitre
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42 * Removed hard-coded value of #18 when adding back sectors per track and replaced
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43 * with the appropriate value: ddtks,u
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44
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45 nam Boot
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46 ttl WD1773 Boot module
0
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47
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48 IFP1
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49 use defsfile
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50 ENDC
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51
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52 * FDC Control Register bits at $FF40
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53 HALTENA equ %10000000
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54 SIDESEL equ %01000000 DRVSEL3 if no DS drives
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55 DDEN equ %00100000
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56 READY equ %00010000 READY for Tandy WD1773-based controllers
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57 MOTON equ %00001000
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58 DRVSEL2 equ %00000100
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59 DRVSEL1 equ %00000010
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60 DRVSEL0 equ %00000001
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61
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62 * Default Boot is from drive 0
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63 BootDr set DRVSEL0
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64 IFEQ DNum-1
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65 BootDr set DRVSEL1 Alternate boot from drive 1
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66 ENDC
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67 IFEQ DNum-2
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68 BootDr set DRVSEL2 Alternate boot from drive 2
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69 ENDC
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70 IFEQ DNum-3
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71 BootDr set SIDESEL Alternate boot from drive 3
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72 ENDC
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73
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74 * WD17x3 DPort offsets
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75 CONTROL equ 0
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76 CMDREG equ 8+0 write-only
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77 STATREG equ CMDREG read-only
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78 TRACKREG equ 8+1
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79 SECTREG equ 8+2
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80 DATAREG equ 8+3
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81
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82 * Sector Size
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83 SECTSIZE equ 256
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84
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85 * Step Rates:
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86 * $00 = 6ms
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87 * $01 = 12ms
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88 * $02 = 20ms
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89 * $03 = 30ms
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90 IFNDEF STEP
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91 STEP set $00
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92 ENDC
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93
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94 tylg set Systm+Objct
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95 atrv set ReEnt+rev
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96 rev set $00
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97 edition set 9
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98
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99 mod eom,name,tylg,atrv,start,size
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100
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101 * NOTE: these are U-stack offsets, not DP
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102 seglist rmb 2 pointer to segment list
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103 blockloc rmb 2 pointer to memory requested
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104 blockimg rmb 2 duplicate of the above
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105 bootsize rmb 2 size in bytes
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106 LSN0Ptr rmb 2 In memory LSN0 pointer
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107 drvsel rmb 1
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108 currtrak rmb 1
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109 * Note, for optimization purposes, the following two variables
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110 * should be adjacent!!
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111 ddtks rmb 1 no. of sectors per track
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112 ddfmt rmb 1
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113 side rmb 1 side 2 flag
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114 size equ .
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115
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116 name fcs /Boot/
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117 fcb edition
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118
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119 * Common booter-required defines
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120 LSN24BIT equ 0
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121 FLOPPY equ 1
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122
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123 * HWInit - Initialize the device
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124 * Entry: Y = hardware address
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125 * Exit: Carry Clear = OK, Set = Error
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126 * B = error (Carry Set)
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127 HWInit
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128 lda #%11010000 ($D0) Force Interrupt (stops any command in progress)
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129 sta CMDREG,y write command to command register
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130 lbsr Delay2 delay 54~
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131 lda STATREG,y clear status register
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132 lda #$FF
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133 sta currtrak,u set current track to 255
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134 leax >NMIRtn,pcr point to NMI routine
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135 IFGT Level-1
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136 stx <D.NMI save address
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137 ELSE
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138 stx >D.XNMI+1 save address
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139 lda #$7E
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140 sta >D.XNMI
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141 ENDC
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142 lda #MOTON turn on drive motor
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143 ora WhichDrv,pcr
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144 sta CONTROL,y
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145 * MOTOR ON spin-up delay loop (~307 mSec)
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146 IFGT Level-1
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147 IFNE H6309
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148 ldd #$F000 3 cycles
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149 ELSE
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150 ldd #50000
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151 ENDC
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152 ELSE
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153 ldd #25000
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154 ENDC
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155 * IFNE H6309
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156 * nop
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157 * ENDC
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158 L003A nop 1 cycles
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159 nop 1 cycles
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160 * IFNE H6309
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161 * nop
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162 * nop
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
diff changeset
163 * nop
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
diff changeset
164 * ENDC
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robert
parents: 1886
diff changeset
165 subd #$0001 4 cycles
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robert
parents: 1886
diff changeset
166 bne L003A 3 cycles
1894
6d5bd8549d28 More booter optimizations
boisy
parents: 1893
diff changeset
167 * HWTerm - Terminate the device
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boisy
parents: 1893
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168 * Entry: Y = hardware address
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boisy
parents: 1893
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169 * Exit: Carry Clear = OK, Set = Error
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parents: 1893
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170 * B = error (Carry Set)
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parents: 1893
diff changeset
171 HWTerm clrb
2007
ee587586c0ab Drive motor now shut off before boot module returns to kernel
boisy
parents: 1965
diff changeset
172 stb CONTROL,y turn off all drive motors (BGP)
1894
6d5bd8549d28 More booter optimizations
boisy
parents: 1893
diff changeset
173 rts
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boisy
parents: 1893
diff changeset
174
1893
1827bb446188 Modified booters to use new boot strategy with boot_common.asm
boisy
parents: 1891
diff changeset
175
2049
0cf8513d33d7 Updated for new structure
boisy
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diff changeset
176 use boot_common.asm
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177
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
parents: 201
diff changeset
178
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179 DoDDns lda #DDEN+MOTON double density enable and motor on
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180 ora WhichDrv,pcr OR in selected drive
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181 sta drvsel,u save drive selection byte
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182 clr currtrak,u clear current track
0
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183 lda #$05
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184 lbsr SetTrak Set the track to the head we want
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185 ldb #0+STEP RESTORE cmd
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186 lbra Talk2FDC send command and wait for it to complete
0
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187
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boisy
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188 * HWRead - Read a 256 byte sector from the device
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189 * Entry: Y = hardware address
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190 * B = bits 23-16 of LSN
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191 * X = bits 15-0 of LSN
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192 * blockloc,u = ptr to 256 byte sector
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193 * Exit: X = ptr to data (i.e. ptr in blockloc,u)
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194 * Carry Clear = OK, Set = Error
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195 *
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196 HWRead lda #$91
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197 bsr L00DF else branch subroutine
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198 bcs HWRRts branch if error
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199 ldx blockloc,u get buffer pointer in X for caller
1287
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boisy
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200 clrb
1886
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boisy
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201 HWRRts rts
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202
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203 L00D7 bcc L00DF
0
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204 pshs x,b,a
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diff changeset
205 bsr DoDDns
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206 puls x,b,a
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207 L00DF pshs x,b,a save LSN, command
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208 bsr ReadSect
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209 puls x,b,a restore LSN, command
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210 bcc HWRRts branch if OK
1287
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211 lsra
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diff changeset
212 bne L00D7
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213 ReadSect bsr Seek2Sect seek to the sector stored in X
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214 bcs HWRRts if error, return to caller
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215 ldx blockloc,u get address of buffer to fill
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216 orcc #IntMasks mask interrupts
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217 pshs x save X
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218 ldx #$FFFF
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219 ldb #%10000000 ($80) READ SECTOR command
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220 stb CMDREG,y write to command register
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221 ldb drvsel,u (DDEN+MOTORON+BootDr)
1520
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
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222 * NOTE: The 1773 FDC multiplexes the write precomp enable and ready
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
parents: 1516
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223 * signals on the ENP/RDY pin, so the READY bit must always be ON for
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
parents: 1516
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224 * read and seek commands. (from the FD502 FDC Service Manual)
3130
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225 orb #DDEN+READY set DDEN+READY bits ($30)
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226 tst side,u are we on side 2?
1287
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227 beq L0107
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diff changeset
228 orb #SIDESEL set side 2 bit
1882
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boisy
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229 L0107 stb CONTROL,y
3130
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230 lbsr Delay2 delay 54~
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diff changeset
231 orb #HALTENA HALT enable ($80)
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232 * lda #%00000010 RESTORE cmd ($02)
1516
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boisy
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233 *L0111 bita >DPort+STATREG
1291
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boisy
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234 * bne L0123
92e9f7416fc9 Added BLOB-stop fix, changed one line as per Robert Gault's suggestion
boisy
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235 * leay -$01,y
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boisy
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236 * bne L0111
1515
30c1d42f3913 Added comments, slow optimization progress
boisy
parents: 1514
diff changeset
237 * lda drvsel,u
1520
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boisy
parents: 1516
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238 * sta >DPort+CONTROL
1291
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boisy
parents: 1287
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239 * puls y
92e9f7416fc9 Added BLOB-stop fix, changed one line as per Robert Gault's suggestion
boisy
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diff changeset
240 * bra L0138
1882
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boisy
parents: 1709
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241 stb CONTROL,y
1291
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boisy
parents: 1287
diff changeset
242 nop
92e9f7416fc9 Added BLOB-stop fix, changed one line as per Robert Gault's suggestion
boisy
parents: 1287
diff changeset
243 nop
1882
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boisy
parents: 1709
diff changeset
244 * bra L0123
1516
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boisy
parents: 1515
diff changeset
245
3130
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diff changeset
246 ldx ,s get X saved earlier
1516
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boisy
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diff changeset
247 * Sector READ Loop
3130
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diff changeset
248 L0123 lda DATAREG,y read from WD DATA register
0
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boisy
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249 sta ,x+
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boisy
parents: 1516
diff changeset
250 * stb >DPort+CONTROL
1291
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boisy
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251 nop
1287
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boisy
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diff changeset
252 bra L0123
1520
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boisy
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253 * RVH NOTE: This ONLY works for double density boot disks! The Tandy
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
parents: 1516
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254 * controllers internally gate HALT enable with the DDEN bit, which
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
parents: 1516
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255 * means that reading a single-density boot disk will not generate the
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
parents: 1516
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256 * NMI signal needed to exit the read loop! Single-density disks must
5ff76789bec2 Updated boot_1773.asm from Rodney H.
boisy
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257 * use a polled I/O loop instead.
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diff changeset
258 NMIRtn leas R$Size,s adjust stack
1882
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259 puls x
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260 ldb STATREG,y read WD STATUS register
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diff changeset
261 bitb #$9C any errors?
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262 * bitb #$04 LOST DATA bit set?
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263 beq r@ branch if not
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264 * beq ChkErr branch if not
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265 L0138 comb else we will return error
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
parents: 201
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266 ldb #E$Read
1886
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diff changeset
267 r@ rts
0
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268
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269 Seek2Sect
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270 lda #MOTON permit alternate drives
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271 ora WhichDrv,pcr permit alternate drives
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272 sta drvsel,u save byte to static mem
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273 clr side,u start on side 1
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diff changeset
274 tfr x,d move LSN into D
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275 cmpd #$0000 zero?
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276 beq L016C branch if so
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diff changeset
277 clr ,-s else clear space on stack
2065
3bd91f399082 Login now uses sysgo to get strings.
boisy
parents: 2049
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278 pshs a
3bd91f399082 Login now uses sysgo to get strings.
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279 lda ddfmt,u
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diff changeset
280 bita #FMT.SIDE double sided disk?
2065
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boisy
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281 puls a
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diff changeset
282 beq SnglSid branch if not
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diff changeset
283 bra DblSid
1515
30c1d42f3913 Added comments, slow optimization progress
boisy
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diff changeset
284 * Double-sided code
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diff changeset
285 L0152 com side,u flag side 2
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boisy
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diff changeset
286 bne DblSid
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
parents: 201
diff changeset
287 inc ,s
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diff changeset
288 DblSid subb ddtks,u
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
parents: 201
diff changeset
289 sbca #$00
1287
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290 bcc L0152
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diff changeset
291 bra L0168
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292 L0160 inc ,s
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diff changeset
293 SnglSid subb ddtks,u subtract sectors per track from B
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
parents: 201
diff changeset
294 sbca #$00
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295 bcc L0160
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diff changeset
296 L0168 addb ddtks,u add sectors per track
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diff changeset
297 puls a get current track indicator off of stack
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298 L016C incb
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299 stb SECTREG,y save in sector register
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diff changeset
300 SetTrak ldb currtrak,u get current track in B
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301 stb TRACKREG,y save in track register
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diff changeset
302 cmpa currtrak,u same as A?
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parents: 2770
diff changeset
303 beq rtsok branch if so
1514
b7d6cb1df834 added comments
boisy
parents: 1463
diff changeset
304 sta currtrak,u
1882
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diff changeset
305 sta DATAREG,y
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diff changeset
306 ldb #$10+STEP SEEK command
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diff changeset
307 bsr Talk2FDC send command to controller
0
6641a883d6b0 Initial revision
boisy
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diff changeset
308 pshs x
1520
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boisy
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diff changeset
309 * Seek Delay
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diff changeset
310 ldx #$222E delay ~39 mSec (78mS L1)
1886
b151cc54904e Added fragmented bootfile support. Added more labels and comments
boisy
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diff changeset
311 SeekDly leax -$01,x
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diff changeset
312 bne SeekDly
0
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313 puls x
1886
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boisy
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314 rtsok clrb
1287
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315 rts
1516
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boisy
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316
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317 *ChkErr bitb #$98 evaluate WD status (READY, RNF, CRC err)
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318 * bne L0138
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319 * clrb
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320 * rts
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321
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322 Talk2FDC bsr DoCMD issue FDC cmd, wait 54~
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323 FDCLoop ldb STATREG,y get status
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324 bitb #$01 still BUSY?
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325 bne FDCLoop loop until command completes
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326 rts
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327
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328 * Issue command and wait 54 clocks
1520
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boisy
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329 * Controller requires a min delay of 14uS (DD) or 28uS (SD)
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boisy
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330 * following a command write before status register is valid
1886
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331 DoCMD bsr SelNSend
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boisy
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332 * Delay branches
1520
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boisy
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333 * 54 clock delay including bsr (=30uS/L2,60us/L1)
1891
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
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334 * H6309 code changed to reduce code size, RG
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335 IFEQ H6309
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336 Delay2
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337 lbsr Delay3
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338 Delay3
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339 lbsr Delay4
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340 Delay4
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341 ELSE
1891
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robert
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342 Delay2 lda #5 3 cycles
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robert
parents: 1886
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343 Delay3 exg a,a 5 cycles | 10*5
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robert
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344 deca 2 cycles |
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robert
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345 bne Delay3 3 cycles |
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346 ENDC
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347 rts
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
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348
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349 * Select And Send
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350 * Entry: B = command byte
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351 SelNSend lda drvsel,u
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boisy
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352 sta CONTROL,y
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boisy
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353 stb CMDREG,y
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354 rts
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355
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356 IFGT Level-1
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357 * L2 kernel file is composed of rel, boot, krn. The size of each of these
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358 * is controlled with filler, so that (after relocation):
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359 * rel starts at $ED00 and is $130 bytes in size
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parents: 2770
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360 * boot starts at $EE30 and is $1D0 bytes in size
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parents: 2770
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361 * krn starts at $F000 and ends at $FEFF (there is no 'emod' at the end
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Neal Crook <foofoobedoo@gmail.com>
parents: 2770
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362 * of krn and so there are no module-end boilerplate bytes)
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parents: 2770
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363 *
e0614e08fa5e l1 boot modules: Expand documentation and clean up code
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parents: 2770
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364 * Filler to get to a total size of $1D0. 3, 2, 1 represent bytes after
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parents: 2770
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365 * the filler: the end boilerplate for the module, fdb and fcb respectively.
1882
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boisy
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366 Filler fill $39,$1D0-3-2-1-*
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367 ENDC
0
6641a883d6b0 Initial revision
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368
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boisy
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369 Address fdb DPort
1886
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370 WhichDrv fcb BootDr
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371
0
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372 emod
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373 eom equ *
48
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374 end