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3033
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1 ********************************************************************
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2 * Boot - CoCo SDC Boot module
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3 *
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4 * $Id$
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5 *
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6 * Edt/Rev YYYY/MM/DD Modified by
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7 * Comment
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8 * ------------------------------------------------------------------
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9 * 2014/12/22 Darren Atkinson
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10 * Created.
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11
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12 nam Boot
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13 ttl SDC Boot module
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14
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15 IFP1
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16 use defsfile
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17 ENDC
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18
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19 * Default Boot is from drive 0
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20 BootDr set 0
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21
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22 * Alternate Boot is from drive 1
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23 IFEQ DNum-1
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24 BootDr set 1
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25 ENDC
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26
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27 * Common booter-required defines
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28 LSN24BIT equ 1
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29 FLOPPY equ 0
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30
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31 * DPort offsets
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32 CONTROL equ 0 write-only
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33 CMDREG equ 8+0 write-only
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34 STATREG equ CMDREG read-only
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35 LSNREG equ 8+1
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36 DATAREG equ 8+2
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37
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38 * NOTE: these are U-stack offsets, not DP
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39 seglist rmb 2 pointer to segment list
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40 blockloc rmb 2 pointer to memory requested
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41 blockimg rmb 2 duplicate of the above
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42 bootsize rmb 2 size in bytes
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43 LSN0Ptr rmb 2 In memory LSN0 pointer
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44 size equ .
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45
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46
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47 tylg set Systm+Objct
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48 atrv set ReEnt+rev
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49 rev set $00
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50 edition set 1
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51
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52 mod eom,name,tylg,atrv,start,size
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53
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54 name fcs /Boot/
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55 fcb edition
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56
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57
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58 *--------------------------------------------------------------------------
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59 * HWInit - Initialize the device
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60 *
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61 * Entry:
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62 * Y = hardware address
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63 *
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64 * Exit:
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65 * Carry Clear = OK, Set = Error
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66 * B = error (Carry Set)
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67 *
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68 HWInit orcc #$50 mask interrupts
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69 lda #$D0 stop any emulated FDC command
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70 sta CMDREG,y
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71 pshs d,x,y,u delay
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72 puls d,x,y,u
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73 lda STATREG,y clear INTRQ
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74
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75 *** Fall Thru ***
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76
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77 *--------------------------------------------------------------------------
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78 * HWTerm - Terminate the device
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79 *
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80 * Entry:
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81 * Y = hardware address
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82 *
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83 * Exit:
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84 * Carry Clear = OK, Set = Error
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85 * B = error (Carry Set)
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86 *
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87 HWTerm clrb no error
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88 stb CONTROL,y disable command mode
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89 rts
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90
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91
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92 ***************************************************************************
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93 use boot_common.asm
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94 ***************************************************************************
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95
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96 *
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97 * HWRead - Read a 256 byte sector from the device
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98 *
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99 * Entry:
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100 * Y = hardware address
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101 * B = bits 23-16 of LSN
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102 * X = bits 15-0 of LSN
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103 * blockloc,u = where to load the 256 byte sector
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104 *
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105 * Exit:
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106 * X = ptr to data (i.e. ptr in blockloc,u)
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107 *
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108 HWRead lda #$43 start command mode
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109 sta CONTROL,y
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110 stb LSNREG,y put LSN into registers
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111 stx LSNREG+1,y
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112 clra A=0 for use at rdExit
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113 bsr waitSDC wait for BUSY to be cleared
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114 bcs rdExit exit on error or timeout
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115 ldb WhichDrv,pcr get drive number
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116 andb #1 limit to 0 or 1
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117 orb #$80 combine with Read Sector command
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118 stb CMDREG,y send command to controller
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119 bsr waitSDC wait for data READY
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120 bcs rdExit exit on error or timeout
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121 ldx blockloc,u get address of buffer to fill
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122 pshs u,x preserve U and X
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123 ldb #256/2 1/2 sector size
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124 rdLoop ldu DATAREG,y read word data from controller
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125 stu ,x++ store to buffer
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126 decb decrement word counter
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127 bne rdLoop loop until done
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128 puls x,u restore X and U
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129 rdExit sta CONTROL,y end command mode
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130 rts
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131
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132
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133 *--------------------------------------------------------------------------
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134 * Wait for controller status to indicate either "Not Busy" or "Ready".
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135 * Will time out if neither condition satisfied within a suitable period.
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136 *
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137 * Exit:
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138 * CC.C set on error or time out
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139 *
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140 waitSDC ldx #0 setup timeout counter
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141 waitLp bsr waitRet extra cycles for timeout
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142 comb set carry for timeout/FAILED
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143 leax ,-x decrement timeout counter
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144 beq waitRet return if timed out
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145 ldb STATREG,y read status
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146 bmi waitRet return if FAILED
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147 lsrb BUSY --> Carry
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148 bcc waitRet return if not busy
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149 rolb clear carry
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150 bitb #2 test READY
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151 beq waitLp loop if not ready for transfer
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152 waitRet rts return
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153
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154
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155 *--------------------------------------------------------------------------
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156
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157 IFGT Level-1
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158 * Filler to get $1D0
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159 Filler fill $39,$1D0-3-2-1-*
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160 ENDC
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161
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162 Address fdb DPort
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163 WhichDrv fcb BootDr
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164
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165 emod
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166 eom equ *
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167 end
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