Mercurial > hg > Members > kono > nitros9-code

annotate level1/modules/boot_1773.asm @ 2152:74fb212cb659

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Changelog comes from higher up
author boisy
date Wed, 14 May 2008 02:13:22 +0000
parents 192496d18a9b
children bfe3de781ddf
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1 ********************************************************************
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2 * Boot - WD1773 Boot module
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3 *
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4 * $Id$
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5 *
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6 * Edt/Rev YYYY/MM/DD Modified by
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7 * Comment
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8 * ------------------------------------------------------------------
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9 * 4 1985/??/??
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10 * Original Tandy distribution version.
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11 *
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12 * 6 1998/10/12 Boisy G. Pitre
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13 * Obtained from L2 Upgrade archive, has 6ms step rate and disk timeout
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14 * changes.
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15 *
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16 * 6r2 2003/05/18 Boisy G. Pitre
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17 * Added '.' output for each sector for OS-9 L2 and NitrOS9 for
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18 * Mark Marlette (a special request :).
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19 *
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20 * 6r3 2003/08/31 Robert Gault
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21 * Put BLOB-stop code in place, changed orb #$30 to orb #$28
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22 *
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23 * 6r4 2004/02/17 Rodney Hamilton
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24 * Minor optimizations, improvements in source comments
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25 *
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26 * 7 2005/10/10 Boisy G. Pitre
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27 * Added fragmented bootfile support
2007
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28 *
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29 * 7 2005/10/13 Robert Gault
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30 * Changed timing loops for H6309L2 so that code shortened enough to
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31 * fit within the $1D0 boundary.
2007
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32 *
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33 * 8 2006/03/03 Boisy G. Pitre
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34 * Drive motors now turned off before returning to kernel.
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35 *
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36 * 9 2006/05/05 Boisy G. Pitre
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37 * Fixed bug where single sided booting was broken
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38 *
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39 * 2006/06/04 Boisy G. Pitre
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40 * Removed hard-coded value of #18 when adding back sectors per track and replaced
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41 * with the appropriate value: ddtks,u
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42
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43 nam Boot
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44 ttl WD1773 Boot module
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45
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46 IFP1
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47 use defsfile
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48 ENDC
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49
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50 * FDC Control Register bits at $FF40
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51 HALTENA equ %10000000
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52 SIDESEL equ %01000000 DRVSEL3 if no DS drives
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53 DDEN equ %00100000
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54 READY equ %00010000 READY for Tandy WD1773-based controllers
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55 MOTON equ %00001000
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56 DRVSEL2 equ %00000100
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57 DRVSEL1 equ %00000010
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58 DRVSEL0 equ %00000001
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59
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60 * Default Boot is from drive 0
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61 BootDr set DRVSEL0
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62 IFEQ DNum-1
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63 BootDr set DRVSEL1 Alternate boot from drive 1
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64 ENDC
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65 IFEQ DNum-2
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66 BootDr set DRVSEL2 Alternate boot from drive 2
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67 ENDC
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68 IFEQ DNum-3
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69 BootDr set SIDESEL Alternate boot from drive 3
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70 ENDC
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71
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72 * WD17x3 DPort offsets
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73 CONTROL equ 0
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74 CMDREG equ 8+0 write-only
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75 STATREG equ CMDREG read-only
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76 TRACKREG equ 8+1
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77 SECTREG equ 8+2
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78 DATAREG equ 8+3
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79
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80 * Sector Size
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81 SECTSIZE equ 256
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82
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83 * Step Rates:
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84 * $00 = 6ms
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85 * $01 = 12ms
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86 * $02 = 20ms
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87 * $03 = 30ms
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88 STEP set $00
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89
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90 tylg set Systm+Objct
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91 atrv set ReEnt+rev
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92 rev set $00
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93 edition set 9
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94
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95 mod eom,name,tylg,atrv,start,size
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96
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97 * NOTE: these are U-stack offsets, not DP
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98 seglist rmb 2 pointer to segment list
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99 blockloc rmb 2 pointer to memory requested
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100 blockimg rmb 2 duplicate of the above
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101 bootsize rmb 2 size in bytes
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102 LSN0Ptr rmb 2 In memory LSN0 pointer
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103 drvsel rmb 1
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104 currtrak rmb 1
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105 * Note, for optimization purposes, the following two variables
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106 * should be adjacent!!
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107 ddtks rmb 1 no. of sectors per track
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108 ddfmt rmb 1
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109 side rmb 1 side 2 flag
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110 size equ .
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111
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112 name fcs /Boot/
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113 fcb edition
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114
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115 * Common booter-required defines
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116 LSN24BIT equ 0
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117 FLOPPY equ 1
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118
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119 * HWInit - Initialize the device
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120 * Entry: Y = hardware address
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121 * Exit: Carry Clear = OK, Set = Error
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122 * B = error (Carry Set)
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123 HWInit
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124 lda #%11010000 ($D0) Force Interrupt (stops any command in progress)
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125 sta CMDREG,y write command to command register
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126 lbsr Delay2 delay 54~
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127 lda STATREG,y clear status register
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128 lda #$FF
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129 sta currtrak,u set current track to 255
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130 leax >NMIRtn,pcr point to NMI routine
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131 IFGT Level-1
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132 stx <D.NMI save address
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133 ELSE
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134 stx >D.XNMI+1 save address
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135 lda #$7E
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136 sta >D.XNMI
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137 ENDC
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138 lda #MOTON turn on drive motor
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139 ora WhichDrv,pcr
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140 sta CONTROL,y
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141 * MOTOR ON spin-up delay loop (~307 mSec)
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142 IFGT Level-1
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143 IFNE H6309
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144 ldd #$F000 3 cycles
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145 ELSE
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146 ldd #50000
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147 ENDC
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148 ELSE
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149 ldd #25000
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150 ENDC
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151 * IFNE H6309
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152 * nop
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153 * ENDC
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154 L003A nop 1 cycles
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155 nop 1 cycles
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156 * IFNE H6309
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157 * nop
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158 * nop
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159 * nop
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160 * ENDC
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161 subd #$0001 4 cycles
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162 bne L003A 3 cycles
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163 * HWTerm - Terminate the device
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164 * Entry: Y = hardware address
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165 * Exit: Carry Clear = OK, Set = Error
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166 * B = error (Carry Set)
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167 HWTerm clrb
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168 stb CONTROL,y turn off all drive motors (BGP)
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169 rts
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170
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171
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172 use boot_common.asm
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173
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174
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175 DoDDns lda #DDEN+MOTON double density enable and motor on
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176 ora WhichDrv,pcr OR in selected drive
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177 sta drvsel,u save drive selection byte
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178 clr currtrak,u clear current track
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179 lda #$05
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180 lbsr SetTrak Set the track to the head we want
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181 ldb #0+STEP RESTORE cmd
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182 lbra Talk2FDC send command and wait for it to complete
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183
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184 * HWRead - Read a 256 byte sector from the device
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185 * Entry: Y = hardware address
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186 * B = bits 23-16 of LSN
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187 * X = bits 15-0 of LSN
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188 * blockloc,u = ptr to 256 byte sector
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189 * Exit: X = ptr to data (i.e. ptr in blockloc,u)
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190 HWRead lda #$91
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191 bsr L00DF else branch subroutine
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192 bcs HWRRts branch if error
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193 ldx blockloc,u get buffer pointer in X for caller
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194 clrb
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195 HWRRts rts
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196
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197 L00D7 bcc L00DF
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198 pshs x,b,a
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199 bsr DoDDns
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200 puls x,b,a
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201 L00DF pshs x,b,a save LSN, command
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202 bsr ReadSect
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203 puls x,b,a restore LSN, command
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204 bcc HWRRts branch if OK
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205 lsra
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206 bne L00D7
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207 ReadSect bsr Seek2Sect seek to the sector stored in X
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208 bcs HWRRts if error, return to caller
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209 ldx blockloc,u get address of buffer to fill
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210 orcc #IntMasks mask interrupts
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211 pshs x save X
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212 ldx #$FFFF
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213 ldb #%10000000 ($80) READ SECTOR command
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214 stb CMDREG,y write to command register
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215 ldb drvsel,u (DDEN+MOTORON+BootDr)
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216 * NOTE: The 1773 FDC multiplexes the write precomp enable and ready
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217 * signals on the ENP/RDY pin, so the READY bit must always be ON for
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218 * read and seek commands. (from the FD502 FDC Service Manual)
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219 orb #DDEN+READY set DDEN+READY bits ($30)
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220 tst side,u are we on side 2?
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221 beq L0107
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222 orb #SIDESEL set side 2 bit
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223 L0107 stb CONTROL,y
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224 lbsr Delay2 delay 54~
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225 orb #HALTENA HALT enable ($80)
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226 * lda #%00000010 RESTORE cmd ($02)
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227 *L0111 bita >DPort+STATREG
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228 * bne L0123
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229 * leay -$01,y
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230 * bne L0111
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231 * lda drvsel,u
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232 * sta >DPort+CONTROL
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233 * puls y
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234 * bra L0138
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235 stb CONTROL,y
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236 nop
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237 nop
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238 * bra L0123
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239
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240 ldx ,s get X saved earlier
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241 * Sector READ Loop
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242 L0123 lda DATAREG,y read from WD DATA register
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243 sta ,x+
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244 * stb >DPort+CONTROL
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245 nop
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246 bra L0123
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247 * RVH NOTE: This ONLY works for double density boot disks! The Tandy
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248 * controllers internally gate HALT enable with the DDEN bit, which
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249 * means that reading a single-density boot disk will not generate the
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250 * NMI signal needed to exit the read loop! Single-density disks must
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251 * use a polled I/O loop instead.
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252 NMIRtn leas R$Size,s adjust stack
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253 puls x
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254 ldb STATREG,y read WD STATUS register
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255 bitb #$9C any errors?
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256 * bitb #$04 LOST DATA bit set?
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257 beq r@ branch if not
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258 * beq ChkErr branch if not
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259 L0138 comb else we will return error
210
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260 ldb #E$Read
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261 r@ rts
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262
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263 Seek2Sect
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264 lda #MOTON permit alternate drives
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265 ora WhichDrv,pcr permit alternate drives
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266 sta drvsel,u save byte to static mem
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267 clr side,u start on side 1
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268 tfr x,d move LSN into D
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269 cmpd #$0000 zero?
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270 beq L016C branch if so
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271 clr ,-s else clear space on stack
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272 pshs a
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273 lda ddfmt,u
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274 bita #FMT.SIDE double sided disk?
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275 puls a
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276 beq SnglSid branch if not
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277 bra DblSid
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278 * Double-sided code
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279 L0152 com side,u flag side 2
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280 bne DblSid
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
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281 inc ,s
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282 DblSid subb ddtks,u
210
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283 sbca #$00
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284 bcc L0152
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285 bra L0168
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286 L0160 inc ,s
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287 SnglSid subb ddtks,u subtract sectors per track from B
210
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288 sbca #$00
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289 bcc L0160
2068
192496d18a9b Minor kosher fix
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290 L0168 addb ddtks,u add sectors per track
192496d18a9b Minor kosher fix
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291 puls a get current track indicator off of stack
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292 L016C incb
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293 stb SECTREG,y save in sector register
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294 SetTrak ldb currtrak,u get current track in B
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295 stb TRACKREG,y save in track register
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296 cmpa currtrak,u same as A?
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297 beq rtsok branch if so
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parents: 1463
diff changeset
298 sta currtrak,u
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299 sta DATAREG,y
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300 ldb #$10+STEP SEEK command
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301 bsr Talk2FDC send command to controller
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302 pshs x
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303 * Seek Delay
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304 ldx #$222E delay ~39 mSec (78mS L1)
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305 SeekDly leax -$01,x
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306 bne SeekDly
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307 puls x
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diff changeset
308 rtsok clrb
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309 rts
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310
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311 *ChkErr bitb #$98 evaluate WD status (READY, RNF, CRC err)
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312 * bne L0138
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313 * clrb
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314 * rts
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315
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316 Talk2FDC bsr DoCMD issue FDC cmd, wait 54~
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317 FDCLoop ldb STATREG,y get status
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318 bitb #$01 still BUSY?
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319 bne FDCLoop loop until command completes
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320 rts
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321
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322 * Issue command and wait 54 clocks
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323 * Controller requires a min delay of 14uS (DD) or 28uS (SD)
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324 * following a command write before status register is valid
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325 DoCMD bsr SelNSend
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326 * Delay branches
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327 * 54 clock delay including bsr (=30uS/L2,60us/L1)
1891
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
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328 * H6309 code changed to reduce code size, RG
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
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329 IFEQ H6309
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330 Delay2
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331 lbsr Delay3
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332 Delay3
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333 lbsr Delay4
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334 Delay4
1891
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robert
parents: 1886
diff changeset
335 ELSE
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
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336 Delay2 lda #5 3 cycles
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
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337 Delay3 exg a,a 5 cycles | 10*5
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
robert
parents: 1886
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338 deca 2 cycles |
5f8822fb42e0 shortened H6309L2 code to fit within $1D0 bytes
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339 bne Delay3 3 cycles |
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340 ENDC
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341 rts
210
6bf55704c623 Boot is adapted from OS-9 Level Two boot module, now boots from
boisy
parents: 201
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342
1886
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343 * Select And Send
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344 * Entry: B = command byte
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345 SelNSend lda drvsel,u
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346 sta CONTROL,y
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347 stb CMDREG,y
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348 rts
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349
1166
bb618bed0bdc Miscellaneous source improvements
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parents: 249
diff changeset
350 IFGT Level-1
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351 * Filler to get $1D0
1882
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352 Filler fill $39,$1D0-3-2-1-*
1166
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diff changeset
353 ENDC
0
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354
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355 Address fdb DPort
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356 WhichDrv fcb BootDr
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357
0
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358 emod
6641a883d6b0 Initial revision
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359 eom equ *
48
cdfe69117a2f Cleaned up source
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parents: 0
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360 end