Mercurial > hg > Members > kono > nitros9-code
annotate defs/dgndefs @ 1728:843c3687eabd
Additional Dragon changes from Phill Harvey-Smith
author | boisy |
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date | Wed, 17 Nov 2004 01:22:14 +0000 |
parents | 78ce0a5ffc8e |
children | e6e8a44ab20a |
rev | line source |
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1727
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Incorporated changes and additions made by Phill Harvey-Smith for the
boisy
parents:
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1 * |
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Incorporated changes and additions made by Phill Harvey-Smith for the
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2 * Deinitions for ports on Dragon 32/64/Alpha. |
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Incorporated changes and additions made by Phill Harvey-Smith for the
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parents:
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3 * |
1728 | 4 * 2004/11/16. P.Harvey-Smith. |
5 * Fixed the stupid error I made in the defines below | |
6 * that made all the non DPxxxxx defines equal to FF00 !!! | |
7 * | |
1727
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Incorporated changes and additions made by Phill Harvey-Smith for the
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8 |
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9 IO equ $ff00 ; IO page on Dragon |
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10 |
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11 * |
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12 * Most of these symbols will be defined twice, as some |
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Incorporated changes and additions made by Phill Harvey-Smith for the
boisy
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13 * of the Dragon code, sets DP=$FF, and uses direct page |
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14 * addressing to access the io ports, whilst some of it |
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15 * uses absolute addressing. |
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16 * The versions starting DP must be used with DP=$FF. |
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17 * |
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18 |
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19 *Pia 0 and 1 standard on all Dragons. |
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20 |
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Incorporated changes and additions made by Phill Harvey-Smith for the
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21 DPPIA0DA EQU $00 ; Side A Data/DDR |
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22 DPPIA0CRA EQU $01 ; Side A Control. |
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parents:
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23 DPPIA0DB EQU $02 ; Side B Data/DDR |
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boisy
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24 DPPIA0CRB EQU $03 ; Side B Control. |
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25 |
1728 | 26 PIA0DA EQU DPPIA0DA+IO ; Side A Data/DDR |
27 PIA0CRA EQU DPPIA0CRA+IO ; Side A Control. | |
28 PIA0DB EQU DPPIA0DB+IO ; Side A Data/DDR | |
29 PIA0CRB EQU DPPIA0CRB+IO ; Side A Control. | |
1727
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30 |
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31 DPPIA1DA EQU $20 ; Side A Data/DDR |
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32 DPPIA1CRA EQU $21 ; Side A Control. |
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33 DPPIA1DB EQU $22 ; Side B Data/DDR |
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34 DPPIA1CRB EQU $23 ; Side B Control. |
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35 |
1728 | 36 PIA1DA EQU DPPIA1DA+IO ; Side A Data/DDR |
37 PIA1CRA EQU DPPIA1CRA+IO ; Side A Control. | |
38 PIA1DB EQU DPPIA1DB+IO ; Side A Data/DDR | |
39 PIA1CRB EQU DPPIA1CRB+IO ; Side A Control. | |
1727
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40 |
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41 * Dragon Alpha has a third PIA at FF24. |
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42 |
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43 DPPIA2DA EQU $24 ; Side A Data/DDR |
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44 DPPIA2CRA EQU $25 ; Side A Control. |
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boisy
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45 DPPIA2DB EQU $26 ; Side B Data/DDR |
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boisy
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46 DPPIA2CRB EQU $27 ; Side B Control. |
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47 |
1728 | 48 PIA2DA EQU DPPIA2DA+IO ; Side A Data/DDR |
49 PIA2CRA EQU DPPIA2CRA+IO ; Side A Control. | |
50 PIA2DB EQU DPPIA2DB+IO ; Side A Data/DDR | |
51 PIA2CRB EQU DPPIA2CRB+IO ; Side A Control. | |
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52 |
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53 ;WD2797 Floppy disk controler, used in Alpha Note registers in reverse order ! |
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Incorporated changes and additions made by Phill Harvey-Smith for the
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54 DPCmdRegA EQU $2F ; command/status |
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55 DPTrkRegA EQU $2E ; Track register |
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56 DPSecRegA EQU $2D ; Sector register |
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57 DPDataRegA EQU $2C ; Data register |
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58 |
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59 CmdRegA EQU DPCMDREG+IO ; command/status |
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60 TrkRegA EQU DPTRKREG+IO ; Track register |
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61 SecRegA EQU DPSECREG+IO ; Sector register |
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62 DataRegA EQU DPDATAREG+IO ; Data register |
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63 |
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64 ; Constants for Alpha AY-8912 sound chip, which is used to control |
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65 ; Drive select and motor on the Alpha |
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66 |
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67 AYIOREG EQU $0E ; AY-8912, IO Register number. |
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68 AYIdle EQU $00 ; Make AY Idle. |
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69 AYWriteReg EQU $01 ; Write AY Register |
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70 AYReadReg EQU $02 ; Read AY Register |
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71 AYREGLatch EQU $03 ; Latch register into AY |
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72 |
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73 DSMask EQU $03 ; Drive select mask. |
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74 MotorMask EQU $04 ; Motor enable mask |
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75 DDENMask EQU $08 ; DDEN Mask |
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76 ENPMask EQU $10 ; Enable Precomp mask |
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77 NMIMask EQU $20 ; NMI enable Mask |
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78 |
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79 ; Dragon 64/Alpha Serial port. |
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80 DPAciaData EQU $04 ; Acia Rx/Tx Register |
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81 DPAciaStat EQU $05 ; Acia status register |
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82 DPAciaCmd EQU $06 ; Acia command register |
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83 DPAciaCtrl EQU $07 ; Acia control register |
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84 |
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85 ;DragonDos Cartrage IO for WD2797 |
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86 |
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87 ;WD2797 Floppy disk controler, used in DragonDos. |
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88 DPCmdRegD EQU $40 ; command/status |
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boisy
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89 DPTrkRegD EQU $41 ; Track register |
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90 DPSecRegD EQU $42 ; Sector register |
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91 DPDataRegD EQU $43 ; Data register |
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92 |
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93 CmdRegD EQU DPCMDREG+IO ; command/status |
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94 TrkRegD EQU DPTRKREG+IO ; Track register |
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boisy
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95 SecRegD EQU DPSECREG+IO ; Sector register |
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boisy
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96 DataRegD EQU DPDATAREG+IO ; Data register |
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97 |
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98 DPDSKCTL EQU $48 ; Disk DS/motor control reg |
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Incorporated changes and additions made by Phill Harvey-Smith for the
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99 DSKCTL EQU DPDSKCTL+IO |
1728 | 100 |
101 ; Disk IO bitmasks (DragonDos). | |
102 | |
103 NMIEnD EQU %00100000 | |
104 WPCEnD EQU %00010000 | |
105 SDensEnD EQU %00001000 | |
106 MotorOnD EQU %00000100 | |
107 Drive0D EQU %00000000 | |
108 Drive1D EQU %00000001 | |
109 Drive2D EQU %00000010 | |
110 Drive3D EQU %00000011 | |
111 | |
112 | |
113 ; Disk IO bitmasks (Dragon Alpha). | |
114 | |
115 NMIEnA EQU %10000000 ; This is just a guess, but in current code just used as a flag | |
116 WPCEnA EQU %01000000 ; Acording to circuit trace by R.Harding. | |
117 SDensEnA EQU %00000000 ; DDen is pulled low on the alpha, so always enabled. | |
118 MotorOnA EQU %00010000 | |
119 Drive0A EQU %00000001 | |
120 Drive1A EQU %00000010 | |
121 Drive2A EQU %00000100 | |
122 Drive3A EQU %00001000 |