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annotate level1/modules/boot_sdc.asm @ 3132:9bb0c42d9fc6

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Rename remaining Makefiles to makefile for consistency
author Neal Crook <foofoobedoo@gmail.com>
date Fri, 13 Jan 2017 19:52:26 +0000
parents e0614e08fa5e
children
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1 ********************************************************************
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2 * Boot - CoCo SDC Boot module
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3 * Provides HWInit, HWTerm, HWRead which are called by code in
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4 * "use"d boot_common.asm
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5 *
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6 * $Id$
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7 *
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8 * Edt/Rev YYYY/MM/DD Modified by
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9 * Comment
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10 * ------------------------------------------------------------------
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11 * 2014/12/22 Darren Atkinson
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12 * Created.
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13
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14 nam Boot
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15 ttl SDC Boot module
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16
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17 IFP1
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18 use defsfile
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19 ENDC
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20
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21 * Default Boot is from drive 0
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22 BootDr set 0
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23
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24 * Alternate Boot is from drive 1
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25 IFEQ DNum-1
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26 BootDr set 1
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27 ENDC
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28
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29 * Common booter-required defines
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30 LSN24BIT equ 1
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31 FLOPPY equ 0
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32
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33 * DPort offsets
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34 CONTROL equ 0 write-only
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35 CMDREG equ 8+0 write-only
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36 STATREG equ CMDREG read-only
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37 LSNREG equ 8+1
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38 DATAREG equ 8+2
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39
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40 * NOTE: these are U-stack offsets, not DP
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41 seglist rmb 2 pointer to segment list
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42 blockloc rmb 2 pointer to memory requested
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43 blockimg rmb 2 duplicate of the above
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44 bootsize rmb 2 size in bytes
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45 LSN0Ptr rmb 2 In memory LSN0 pointer
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46 size equ .
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47
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48
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49 tylg set Systm+Objct
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50 atrv set ReEnt+rev
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51 rev set $00
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52 edition set 1
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53
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54 mod eom,name,tylg,atrv,start,size
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55
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56 name fcs /Boot/
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57 fcb edition
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58
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59
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60 *--------------------------------------------------------------------------
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61 * HWInit - Initialize the device
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62 *
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63 * Entry:
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64 * Y = hardware address
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65 *
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66 * Exit:
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67 * Carry Clear = OK, Set = Error
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68 * B = error (Carry Set)
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69 *
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70 HWInit
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71 IFNE mc09
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72 clrb
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73 rts
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74 ELSE
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75 orcc #$50 mask interrupts
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76 lda #$D0 stop any emulated FDC command
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77 sta CMDREG,y
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78 pshs d,x,y,u delay
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79 puls d,x,y,u
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80 lda STATREG,y clear INTRQ
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81
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82 *** Fall Thru ***
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83 ENDC
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84 *--------------------------------------------------------------------------
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85 * HWTerm - Terminate the device
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86 *
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87 * Entry:
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88 * Y = hardware address
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89 *
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90 * Exit:
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91 * Carry Clear = OK, Set = Error
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92 * B = error (Carry Set)
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93 *
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94 HWTerm clrb no error
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95 IFNE mc09
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96 ELSE
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97 stb CONTROL,y disable command mode
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98 ENDC
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99 rts
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100
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101
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102 ***************************************************************************
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103 use boot_common.asm
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104 ***************************************************************************
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105
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106 *
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107 * HWRead - Read a 256 byte sector from the device
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108 *
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109 * Entry:
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110 * Y = hardware address
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111 * B = bits 23-16 of LSN
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112 * X = bits 15-0 of LSN
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113 * blockloc,u = where to load the 256 byte sector
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114 *
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115 * Exit:
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116 * X = ptr to data (i.e. ptr in blockloc,u)
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117 * Carry Clear = OK, Set = Error
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118 *
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119 * multicomp09:
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120 * for now, the image starts at SDcard block $02.8000
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121 * so simply need to add that offset to the incoming
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122 * LSN and load it into the hardware. Simples!
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123 HWRead
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124 IFNE mc09
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125 bsr LDSDADRS set up address
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126 * WAIT FOR PREVIOUS COMMAND (IF ANY) TO COMPLETE
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127 RDBIZ LDA SDCTL
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128 CMPA #$80
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129 BNE RDBIZ
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130
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131 * ISSUE THE READ COMMAND TO THE SDCARD CONTROLLER
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132 CLRA
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133 STA SDCTL
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134
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135 * TRANSFER 512 BYTES, WAITING FOR EACH IN TURN. ONLY WANT 256
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136 * OF THEM - DISCARD THE REST
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137
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138 ldx blockloc,u get address of buffer to fill
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139 pshs x
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140 CLRB ZERO IS LIKE 256
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141 SDRBIZ LDA SDCTL
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142 CMPA #$E0
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143 BNE SDRBIZ BYTE NOT READY
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144 LDA SDDATA GET BYTE
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145 STA ,X+ STORE IN SECTOR BUFFER
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146 DECB
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147 BNE SDRBIZ NEXT
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148
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149 SDRBIZ2 LDA SDCTL B IS ALREADY ZERO (LIKE 256)
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150 CMPA #$E0
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151 BNE SDRBIZ2 BYTE NOT READY
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152 LDA SDDATA GET BYTE (BUT DO NOTHING WITH IT)
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153 DECB
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154 BNE SDRBIZ2 NEXT
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155
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156 puls x
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157 clra carry clear -> successful completion
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158 RTS
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159
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160 ELSE
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161 lda #$43 start command mode
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162 sta CONTROL,y
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163 stb LSNREG,y put LSN into registers
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164 stx LSNREG+1,y
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165 clra A=0 for use at rdExit
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166 bsr waitSDC wait for BUSY to be cleared
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167 bcs rdExit exit on error or timeout
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168 ldb WhichDrv,pcr get drive number
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169 andb #1 limit to 0 or 1
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170 orb #$80 combine with Read Sector command
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171 stb CMDREG,y send command to controller
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172 bsr waitSDC wait for data READY
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173 bcs rdExit exit on error or timeout
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174 ldx blockloc,u get address of buffer to fill
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175 pshs u,x preserve U and X
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176 ldb #256/2 1/2 sector size
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177 rdLoop ldu DATAREG,y read word data from controller
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178 stu ,x++ store to buffer
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179 decb decrement word counter
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180 bne rdLoop loop until done
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181 puls x,u restore X and U
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182 rdExit sta CONTROL,y end command mode
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183 rts
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184 ENDC
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185
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186 IFNE mc09
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187 *******************************************************************
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188 * SET SDLBA2 SDLBA1 SDLBA0 FOR NEXT SD OPERATION
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189 * add $02.8000 to {B,XH,XL} and load into the hardware
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190 * registers.
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191 * Can destroy A, B, X, CC
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192 * Assumption: the lowest byte of the adder ($02.8000 here) will
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193 * always be 0 and so never need fixup
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194 LDSDADRS pshs b
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195 tfr x,d
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196 stb SDLBA0 ls byte is done.
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197
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198 ldb #$02
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199
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200 adda #$80
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201 sta SDLBA1 middle byte is done
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202
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203 adcb #$00 add carry from middle byte
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204 addb ,s+ add and drop stacked b
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205 stb SDLBA2
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206 rts
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207 ELSE
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208
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209 *--------------------------------------------------------------------------
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210 * Wait for controller status to indicate either "Not Busy" or "Ready".
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211 * Will time out if neither condition satisfied within a suitable period.
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212 *
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213 * Exit:
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214 * CC.C set on error or time out
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215 *
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216 waitSDC ldx #0 setup timeout counter
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217 waitLp bsr waitRet extra cycles for timeout
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218 comb set carry for timeout/FAILED
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219 leax ,-x decrement timeout counter
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220 beq waitRet return if timed out
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221 ldb STATREG,y read status
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222 bmi waitRet return if FAILED
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223 lsrb BUSY --> Carry
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224 bcc waitRet return if not busy
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225 rolb clear carry
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226 bitb #2 test READY
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227 beq waitLp loop if not ready for transfer
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228 waitRet rts return
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229 ENDC
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230
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231
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232 *--------------------------------------------------------------------------
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233
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234 IFGT Level-1
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235 * L2 kernel file is composed of rel, boot, krn. The size of each of these
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236 * is controlled with filler, so that (after relocation):
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237 * rel starts at $ED00 and is $130 bytes in size
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238 * boot starts at $EE30 and is $1D0 bytes in size
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239 * krn starts at $F000 and ends at $FEFF (there is no 'emod' at the end
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240 * of krn and so there are no module-end boilerplate bytes)
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241 *
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242 * Filler to get to a total size of $1D0. 3, 2, 1 represent bytes after
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243 * the filler: the end boilerplate for the module, fdb and fcb respectively.
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244 Filler fill $39,$1D0-3-2-1-*
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245 ENDC
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246
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247 Address fdb DPort
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248 WhichDrv fcb BootDr
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249
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250 emod
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251 eom equ *
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252 end