annotate level2/modules/sio.asm @ 615:9c923ba45566

Added proper baud delay rates for most, but not all baud rates
author boisy
date Wed, 27 Nov 2002 23:03:39 +0000
parents b3bfa479f8d0
children 5ed7f616e80b
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1 ********************************************************************
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2 * SIO - CoCo 3 Serial driver
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3 *
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4 * $Id$
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5 *
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6 * Ed. Comments Who YY/MM/DD
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7 * ------------------------------------------------------------------
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8 * 9 Original Tandy L2 distribution version
615
9c923ba45566 Added proper baud delay rates for most, but not all baud rates
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9 * 10 Added baud delay table for NitrOS-9
0
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10
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11 nam SIO
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12 ttl CoCo 3 Serial driver
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13
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14 * Disassembled 98/08/23 20:58:36 by Disasm v1.6 (C) 1988 by RML
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15
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16 ifp1
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17 use defsfile
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18 endc
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19
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20 tylg set Drivr+Objct
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21 atrv set ReEnt+rev
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22 rev set $01
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23 edition set 9
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24
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25 mod eom,name,tylg,atrv,start,size
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26
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27 u0000 rmb 29
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28 u001D rmb 1
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29 u001E rmb 1
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30 u001F rmb 1
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31 u0020 rmb 2
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32 u0022 rmb 2
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33 u0024 rmb 1
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34 u0025 rmb 1
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35 size equ .
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36 fcb $03
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37
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38 name fcs /SIO/
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39 fcb edition
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40
615
9c923ba45566 Added proper baud delay rates for most, but not all baud rates
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41 * Baud Rate Delay Table
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42 DelayTbl
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43 IFEQ NitrOS9
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44 * OS-9 Level Two delay values (1.89MHz)
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45 fdb $090C 110 baud
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46 fdb $034C 300 baud
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47 fdb $01A2 600 baud
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48 fdb $00CE 1200 baud
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49 fdb $0062 2400 baud
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50 fdb $002E 4800 baud
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51 fdb $0012 9600 baud
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52 fdb $0003 32000 baud
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53 ELSE
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54 * NitrOS-9 Level Two delay values (1.89MHz)
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55 fdb $090C 110 baud (Unchanged, unknown)
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56 fdb $03D0 300 baud
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57 fdb $01A2 600 baud (Unchanged, unknown)
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58 fdb $00F0 1200 baud
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59 fdb $0073 2400 baud
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60 fdb $0036 4800 baud
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61 fdb $0017 9600 baud
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62 fdb $0003 32000 baud (Unchanged, unknown)
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63 ENDC
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64
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65 start lbra Init
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66 lbra Read
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67 lbra Write
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68 lbra GetStat
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69 lbra SetStat
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70 lbra Term
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71
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72 * Init
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73 *
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74 * Entry:
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75 * Y = address of device descriptor
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76 * U = address of device memory area
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77 *
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78 * Exit:
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79 * CC = carry set on error
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80 * B = error code
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81 *
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82 Init pshs cc
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83 orcc #IntMasks
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84 ldx #PIA1Base
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85 clr $01,x
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86 ldd <IT.COL,y get col/row bytes
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87 std <u0024,u
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88 lda #$FE
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89 sta ,x
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90 lda #$36
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91 sta $01,x
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92 lda ,x
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93 ldd <IT.PAR,y get parity/baud
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94 lbsr L0148
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95 puls cc
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96 clrb
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97
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98 * Term
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99 *
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100 * Entry:
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101 * U = address of device memory area
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102 *
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103 * Exit:
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104 * CC = carry set on error
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105 * B = error code
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106 *
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107 Term rts
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108
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109 * Read
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110 *
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111 * Entry:
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112 * Y = address of path descriptor
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113 * U = address of device memory area
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114 *
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115 * Exit:
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116 * A = character read
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117 * CC = carry set on error
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118 * B = error code
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119 *
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120 Read bsr L00AC
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121 bcs L00C8
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122 ldb #$08
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123 pshs b,cc
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124 tst <u001E,u
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125 beq L0066
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126 dec $01,s
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127 L0066 bra L0077
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128 L0068 lda <PD.BAU,y
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129 anda #$0F
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130 cmpa #$07
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131 beq L0077
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132 ldx #$0001
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133 os9 F$Sleep
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134 L0077 pshs y
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135 ldy #$FFFF
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136 L007D lda >PIA1Base+2
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137 leay -$01,y
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138 beq L008B
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139 lsra
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140 bcs L007D
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141 puls y
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142 bra L0090
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143 L008B puls y
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144 lsra
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145 bcs L0068
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146 L0090 orcc #IntMasks
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147 clra
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148 bsr L00D5
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149 L0095 bsr L00CE
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150 ldb >PIA1Base+2
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151 lsrb
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152 rora
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153 dec $01,s
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154 bne L0095
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155 bsr L00D5
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156 tst <u001E,u
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157 beq L00A8
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158 lsra
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159 L00A8 puls b,cc
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160 clrb
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161 rts
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162 L00AC pshs a
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163 lda <PD.BAU,y
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164 anda #$0F
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165 cmpa #$08
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166 bcc L00C4
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167 lsla
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168 leax >DelayTbl,pcr
0
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169 ldd a,x
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170 std <u0020,u
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171 clrb
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172 puls pc,a
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173 L00C4 ldb #E$BMode
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174 puls a
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175 L00C8 orcc #Carry
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176 rts
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177 L00CB stb >PIA1Base
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178 L00CE pshs b,a
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179 ldd <u0020,u
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180 bra L00DC
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181 L00D5 pshs b,a
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182 ldd <u0020,u
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183 lsra
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184 rorb
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185 L00DC subd #$0001
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186 bne L00DC
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187 puls pc,b,a
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188
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189 * Write
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190 *
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191 * Entry:
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192 * A = character to write
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193 * Y = address of path descriptor
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194 * U = address of device memory area
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195 *
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196 * Exit:
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197 * CC = carry set on error
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198 * B = error code
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199 *
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200 Write bsr L00AC
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201 bcs L00C8
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202 ldb #$09
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203 pshs b,cc
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204 orcc #IntMasks
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205 tst <u001E,u
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206 beq L00F4
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207 dec $01,s
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208 L00F4 andcc #^Carry
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209 L00F6 ldb #$02
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210 bcs L00FB
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211 clrb
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212 L00FB bsr L00CB
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213 lsra
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214 dec $01,s
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215 bne L00F6
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216 ldb <u001D,u
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217 beq L010B
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218 andb #$FE
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219 bsr L00CB
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220 L010B ldb #$02
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221 bsr L00CB
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222 tst <u001F,u
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223 beq L0118
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224 ldb #$02
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225 bsr L00CB
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226 L0118 puls pc,b,cc
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227
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228 * GetStat
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229 *
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230 * Entry:
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231 * A = function code
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232 * Y = address of path descriptor
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233 * U = address of device memory area
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234 *
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235 * Exit:
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236 * CC = carry set on error
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237 * B = error code
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238 *
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239 GetStat cmpa #SS.EOF
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240 bne L0120
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241 L011E clrb
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242 rts
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243 L0120 ldx PD.RGS,y
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244 cmpa #SS.ScSiz
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245 beq L0131
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246 cmpa #SS.ComSt
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247 bne L017E
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248 ldd <u0022,u
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249 std R$Y,x
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250 bra L011E
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251 L0131 ldx PD.RGS,y
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252 clra
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253 ldb <u0024,u
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254 std R$X,x
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255 ldb <u0025,u
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parents:
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256 std R$Y,x
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257 bra L011E
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258
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259 * SetStat
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260 *
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261 * Entry:
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262 * A = function code
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263 * Y = address of path descriptor
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264 * U = address of device memory area
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265 *
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266 * Exit:
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267 * CC = carry set on error
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268 * B = error code
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269 *
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270 SetStat cmpa #SS.ComSt
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271 bne L017E
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272 ldx PD.RGS,y
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273 ldd R$Y,x
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274 L0148 std <u0022,u
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275 clra
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276 clrb
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277 std <u001D,u
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278 sta <u001F,u
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279 ldd <u0022,u
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280 tstb
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281 bpl L015C
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parents:
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282 inc <u001F,u
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283 L015C bitb #$40
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284 bne L017A
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285 bitb #$20
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286 beq L0167
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parents:
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287 inc <u001E,u
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288 L0167 bita #$20
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289 beq L0179
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290 bita #$80
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parents:
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291 beq L017A
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parents:
diff changeset
292 inc <u001D,u
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parents:
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293 bita #$40
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parents:
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294 bne L0179
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parents:
diff changeset
295 inc <u001D,u
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296 L0179 rts
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297 L017A comb
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298 ldb #E$BMode
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299 rts
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300 L017E comb
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diff changeset
301 ldb #E$UnkSvc
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parents:
diff changeset
302 rts
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parents:
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303
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parents:
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304 emod
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305 eom equ *
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306 end