annotate level1/modules/boot_dw3.asm @ 2624:b8c7b7fbf3c9

Major changes: o os9defs, rbfdefs, scfdefs now os9.d, rbf.d, and scf.d o vtiodefs now broken into cocovtio.d (for coco and dragon) and atarivtio.d o systype now broken into coco.d, dragon.d and atari.d o all references to the above in other files have changed
author Boisy Pitre <boisy.pitre@nuance.com>
date Fri, 24 Feb 2012 08:51:08 -0600
parents 27f07aa0bca0
children
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1 ********************************************************************
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2 * Boot - DriveWire 3 Boot Module
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3 *
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4 * $Id$
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5 *
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6 * Edt/Rev YYYY/MM/DD Modified by
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7 * Comment
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8 * ------------------------------------------------------------------
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9 * 1 2008/02/09 Boisy G. Pitre
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10 * Created.
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11
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12 NAM Boot
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13 TTL DriveWire Boot Module
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14
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15 IFP1
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16 USE defsfile
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17 USE drivewire.d
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18 ENDC
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19
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20 tylg SET Systm+Objct
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21 atrv SET ReEnt+rev
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22 rev SET 0
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23 edition SET 1
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24
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25 MOD eom,name,tylg,atrv,start,size
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26
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27 * on-stack buffer to use
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28 ORG 0
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29 seglist RMB 2 pointer to segment list
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30 blockloc RMB 2 pointer to memory requested
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31 blockimg RMB 2 duplicate of the above
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32 bootloc RMB 3 sector pointer; not byte pointer
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33 bootsize RMB 2 size in bytes
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34 LSN0Ptr RMB 2 LSN0 pointer
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35 size EQU .
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36
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37 name EQU *
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38 FCS /Boot/
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39 FCB edition
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40
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41
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42 * Common booter-required defines
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43 LSN24BIT EQU 1
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44 FLOPPY EQU 0
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45
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46
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47 USE boot_common.asm
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48
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49
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50 ************************************************************
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51 ************************************************************
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52 * Hardware-Specific Booter Area *
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53 ************************************************************
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54 ************************************************************
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55
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56 * HWInit - Initialize the device
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57 * Entry: Y = hardware address
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58 * Exit: Carry Clear = OK, Set = Error
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59 * B = error (Carry Set)
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60 HWInit
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61 * Set up DDR for side B
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62 * ldx #PIA1Base get base address of PIA
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63 * ldb 3,x
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64 * andb #%11111011
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65 * stb 3,x
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66 * lda #%11111010
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67 * sta 2,x
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68 * orb #%00000100
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69 * stb 3,x
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70
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71 * Set up DDR for side A
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72 * ldb 1,x
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73 * andb #%11111011
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74 * stb 1,x $FF20 is now Data Direction Register
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75 * lda #%11111110 data direction bits (1=out, 0=in)
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76 * sta ,x tell HW
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77 * orb #%00000100 reset $FF20 to I/O register
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78 * stb 1,x $FF20 is now Data Direction Register
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79 HWTerm clrb
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80 rts
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81
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82
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83 * HWRead - Read a 256 byte sector from the device
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84 * Entry: Y = hardware address
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85 * B = bits 23-16 of LSN
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86 * X = bits 15-0 of LSN
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87 * blockloc,u = ptr to 256 byte sector
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88 * Exit: X = ptr to data (i.e. ptr in blockloc,u)
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89 HWRead
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90 pshs cc,d,x
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91 * Send out op code and 3 byte LSN
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92 lda #OP_READEX load A with READ opcode
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93 Read2 ldb WhichDrv,pcr
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94 std ,s
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95 leax ,s
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96 ldy #5
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97 lbsr DWWrite send it to server
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98 * Get 256 bytes of sector data
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99 ldx blockloc,u
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100 ldy #256
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101 bsr DWRead read bytes from server
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102 bcs ReadEr branch if framing error
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103 bne ReadEr2
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104
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105 * Send two byte checksum
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106 pshs y
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107 leax ,s
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108 ldy #2
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109 lbsr DWWrite
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110 ldy #1
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111 bsr DWRead
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112 leas 2,s
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113 bcs ReadEx
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114 bne ReadEr2
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115 ldb ,s
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116 beq ReadEx
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117 cmpb #E_CRC
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118 bne ReadEr
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119 lda #OP_REREADEX
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120 bra Read2
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121 ReadEx EQU *
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122 leas 5,s eat stack
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123 ldx blockloc,u
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124 clrb
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125 rts
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126 ReadEr2 ldb #E$Read
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127 ReadEr
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128 leas 5,s eat stack
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129 orcc #Carry
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130 rts
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131
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132 USE dwread.asm
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133 USE dwwrite.asm
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134
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135 IFGT Level-1
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136 Pad FILL $39,$1D0-3-2-1-*
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137 ENDC
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138
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139 Address FDB $0000
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140 WhichDrv FCB $00
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141 EMOD
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142 eom EQU *
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143 END