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annotate level1/modules/dwread.asm @ 2725:c2112f93923a lwtools-port

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o dwio for Atari now uses routines in ROM, so dwread/dwrite stripped of Atari o Added NMI code (as a conditional) to clock
author Boisy Pitre <boisy.pitre@nuance.com>
date Tue, 31 Jul 2012 11:54:02 -0500
parents 22bdfbe8bc68
children bfe3de781ddf
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1 *******************************************************
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2 *
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3 * DWRead
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4 * Receive a response from the DriveWire server.
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5 * Times out if serial port goes idle for more than 1.4 (0.7) seconds.
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6 * Serial data format: 1-8-N-1
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7 * 4/12/2009 by Darren Atkinson
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8 *
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9 * Entry:
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10 * X = starting address where data is to be stored
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11 * Y = number of bytes expected
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12 *
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13 * Exit:
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14 * CC = carry set on framing error, Z set if all bytes received
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15 * X = starting address of data received
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16 * Y = checksum
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17 * U is preserved. All accumulators are clobbered
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18 *
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19
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20
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21 IFNE BECKER
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22
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23 * NOTE: There is no timeout currently on here...
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24 DWRead pshs cc,d,x,u
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25 leau ,x
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26 ldx #$0000
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27 orcc #IntMasks
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28 loop@ ldb $FF41
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29 bitb #$02
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30 beq loop@
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31 ldb $FF42
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32 stb ,u+
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33 abx
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34 leay -1,y
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35 bne loop@
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36
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37 tfr x,y
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38 puls cc
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39 andcc #^Carry
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40 orcc #Zero
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41 puls d,x,u,pc
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42
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43 ELSE
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44 IFNE BAUD38400
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45 *******************************************************
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46 * 38400 bps using 6809 code and timimg
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47 *******************************************************
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48
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49 DWRead clra ; clear Carry (no framing error)
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50 deca ; clear Z flag, A = timeout msb ($ff)
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51 tfr cc,b
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52 pshs u,x,dp,b,a ; preserve registers, push timeout msb
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53 orcc #$50 ; mask interrupts
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54 tfr a,dp ; set direct page to $FFxx
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55 setdp $ff
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56 leau ,x ; U = storage ptr
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57 ldx #0 ; initialize checksum
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58 adda #2 ; A = $01 (serial in mask), set Carry
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59
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60 * Wait for a start bit or timeout
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61 rx0010 bcc rxExit ; exit if timeout expired
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62 ldb #$ff ; init timeout lsb
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63 rx0020 bita <BBIN ; check for start bit
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64 beq rxByte ; branch if start bit detected
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65 subb #1 ; decrement timeout lsb
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66 bita <BBIN
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67 beq rxByte
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68 bcc rx0020 ; loop until timeout lsb rolls under
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69 bita <BBIN
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70 beq rxByte
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71 addb ,s ; B = timeout msb - 1
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72 bita <BBIN
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73 beq rxByte
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74 stb ,s ; store decremented timeout msb
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75 bita <BBIN
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76 bne rx0010 ; loop if still no start bit
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77
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78 * Read a byte
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79 rxByte leay ,-y ; decrement request count
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80 ldd #$ff80 ; A = timeout msb, B = shift counter
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81 sta ,s ; reset timeout msb for next byte
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82 rx0030 exg a,a
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83 nop
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84 lda <BBIN ; read data bit
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85 lsra ; shift into carry
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86 rorb ; rotate into byte accumulator
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87 lda #$01 ; prep stop bit mask
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88 bcc rx0030 ; loop until all 8 bits read
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89
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90 stb ,u+ ; store received byte to memory
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91 abx ; update checksum
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92 ldb #$ff ; set timeout lsb for next byte
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93 anda <BBIN ; read stop bit
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94 beq rxExit ; exit if framing error
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95 leay ,y ; test request count
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96 bne rx0020 ; loop if another byte wanted
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97 lda #$03 ; setup to return SUCCESS
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98
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99 * Clean up, set status and return
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100 rxExit leas 1,s ; remove timeout msb from stack
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101 inca ; A = status to be returned in C and Z
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102 ora ,s ; place status information into the..
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103 sta ,s ; ..C and Z bits of the preserved CC
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104 leay ,x ; return checksum in Y
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105 puls cc,dp,x,u,pc ; restore registers and return
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106 setdp $00
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107
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108
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109 ELSE
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110 IFNE H6309-1
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111 *******************************************************
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112 * 57600 (115200) bps using 6809 code and timimg
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113 *******************************************************
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114
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115 DWRead clra ; clear Carry (no framing error)
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116 deca ; clear Z flag, A = timeout msb ($ff)
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117 tfr cc,b
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118 pshs u,x,dp,b,a ; preserve registers, push timeout msb
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119 orcc #$50 ; mask interrupts
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120 tfr a,dp ; set direct page to $FFxx
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121 setdp $ff
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122 leau ,x ; U = storage ptr
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123 ldx #0 ; initialize checksum
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124 lda #$01 ; A = serial in mask
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125 bra rx0030 ; go wait for start bit
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126
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127 * Read a byte
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128 rxByte leau 1,u ; bump storage ptr
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129 leay ,-y ; decrement request count
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130 lda <BBIN ; read bit 0
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131 lsra ; move bit 0 into Carry
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132 ldd #$ff20 ; A = timeout msb, B = shift counter
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133 sta ,s ; reset timeout msb for next byte
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134 rorb ; rotate bit 0 into byte accumulator
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135 rx0010 lda <BBIN ; read bit (d1, d3, d5)
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136 lsra
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137 rorb
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138 bita 1,s ; 5 cycle delay
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139 bcs rx0020 ; exit loop after reading bit 5
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140 lda <BBIN ; read bit (d2, d4)
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141 lsra
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142 rorb
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143 leau ,u
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144 bra rx0010
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145
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146 rx0020 lda <BBIN ; read bit 6
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147 lsra
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148 rorb
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149 leay ,y ; test request count
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150 beq rx0050 ; branch if final byte of request
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151 lda <BBIN ; read bit 7
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152 lsra
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153 rorb ; byte is now complete
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154 stb -1,u ; store received byte to memory
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155 abx ; update checksum
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156 lda <BBIN ; read stop bit
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157 anda #$01 ; mask out other bits
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158 beq rxExit ; exit if framing error
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159
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160 * Wait for a start bit or timeout
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161 rx0030 bita <BBIN ; check for start bit
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162 beq rxByte ; branch if start bit detected
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163 bita <BBIN ; again
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164 beq rxByte
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165 ldb #$ff ; init timeout lsb
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166 rx0040 bita <BBIN
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167 beq rxByte
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168 subb #1 ; decrement timeout lsb
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169 bita <BBIN
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170 beq rxByte
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171 bcc rx0040 ; loop until timeout lsb rolls under
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172 bita <BBIN
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173 beq rxByte
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174 addb ,s ; B = timeout msb - 1
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175 bita <BBIN
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176 beq rxByte
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177 stb ,s ; store decremented timeout msb
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178 bita <BBIN
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179 beq rxByte
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180 bcs rx0030 ; loop if timeout hasn't expired
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181 bra rxExit ; exit due to timeout
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182
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183 rx0050 lda <BBIN ; read bit 7 of final byte
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184 lsra
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185 rorb ; byte is now complete
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186 stb -1,u ; store received byte to memory
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187 abx ; calculate final checksum
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188 lda <BBIN ; read stop bit
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189 anda #$01 ; mask out other bits
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190 ora #$02 ; return SUCCESS if no framing error
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191
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192 * Clean up, set status and return
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193 rxExit leas 1,s ; remove timeout msb from stack
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194 inca ; A = status to be returned in C and Z
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195 ora ,s ; place status information into the..
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196 sta ,s ; ..C and Z bits of the preserved CC
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197 leay ,x ; return checksum in Y
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198 puls cc,dp,x,u,pc ; restore registers and return
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199 setdp $00
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200
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201
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202 ELSE
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203 *******************************************************
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204 * 57600 (115200) bps using 6309 native mode
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205 *******************************************************
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206
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207 DWRead clrb ; clear Carry (no framing error)
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208 decb ; clear Z flag, B = $FF
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209 pshs u,x,dp,cc ; preserve registers
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210 orcc #$50 ; mask interrupts
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211 * ldmd #1 ; requires 6309 native mode
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212 tfr b,dp ; set direct page to $FFxx
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213 setdp $ff
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214 leay -1,y ; adjust request count
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215 leau ,x ; U = storage ptr
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216 tfr 0,x ; initialize checksum
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217 lda #$01 ; A = serial in mask
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218 bra rx0030 ; go wait for start bit
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219
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220 * Read a byte
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221 rxByte sexw ; 4 cycle delay
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222 ldw #$006a ; shift counter and timing flags
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223 clra ; clear carry so next will branch
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224 rx0010 bcc rx0020 ; branch if even bit number (15 cycles)
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225 nop ; extra (16th) cycle
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226 rx0020 lda <BBIN ; read bit
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227 lsra ; move bit into carry
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228 rorb ; rotate bit into byte accumulator
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229 lda #0 ; prep A for 8th data bit
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230 lsrw ; bump shift count, timing bit to carry
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231 bne rx0010 ; loop until 7th data bit has been read
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232 incw ; W = 1 for subtraction from Y
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233 inca ; A = 1 for reading bit 7
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234 anda <BBIN ; read bit 7
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235 lsra ; move bit 7 into carry, A = 0
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236 rorb ; byte is now complete
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237 stb ,u+ ; store received byte to memory
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238 abx ; update checksum
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239 subr w,y ; decrement request count
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240 inca ; A = 1 for reading stop bit
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241 anda <BBIN ; read stop bit
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242 bls rxExit ; exit if completed or framing error
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243
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244 * Wait for a start bit or timeout
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245 rx0030 clrw ; initialize timeout counter
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246 rx0040 bita <BBIN ; check for start bit
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247 beq rxByte ; branch if start bit detected
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248 addw #1 ; bump timeout counter
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249 bita <BBIN
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250 beq rxByte
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251 bcc rx0040 ; loop until timeout rolls over
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252 lda #$03 ; setup to return TIMEOUT status
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253
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254 * Clean up, set status and return
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255 rxExit beq rx0050 ; branch if framing error
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256 eora #$02 ; toggle SUCCESS flag
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257 rx0050 inca ; A = status to be returned in C and Z
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258 ora ,s ; place status information into the..
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259 sta ,s ; ..C and Z bits of the preserved CC
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260 leay ,x ; return checksum in Y
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261 puls cc,dp,x,u,pc ; restore registers and return
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262 setdp $00
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263
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264 ENDC
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265 ENDC
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266 ENDC