Members/kono/nitros9-code: level1/modules/rb1773.asm annotate

annotate level1/modules/rb1773.asm @ 1737:fdb0dde809d2

Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. After several days of struggling without getting the rb1773 code to work, I found a required small change. It may not affect stock SCII units but my altered unit (512 RAM buffer) definitely needs it. I already new that using TFM to transfer to the RAM buffer is problematic at 2Mhz. On my unit, I also can't use a LDD or STD to the RAM buffer on the board at 2Mhz in native mode. I should say that my unit is right on the unstable edge if I used a two byte transfer and it mostly does not work. To accommodate the above, parts of the read/write code need to be changed for SCII units just in case the hardware mod is not the cause of the instability.

author	boisy
date	Fri, 03 Dec 2004 01:05:27 +0000
parents	93d5b9ff0f4a
children	5469aad825d7

rev	line source
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1 ********************************************************************
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	2 * rb1773 - Western Digital 1773 Disk Controller Driver
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	3 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	4 * $Id$
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	5 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	6 * This driver has been tested with the following controllers:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	7 * - Tandy FD-502 "shortie" disk controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	8 * - Disto Super Controller I
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	9 * - Disto Super Controller II
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	10 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	11 * This driver can also be assembled to support the no-halt feature of
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	12 * the Disto Super Controller II.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	13 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	14 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	15 * A lot of references to **.CYL or <u00B6 using 16 bit registers can be
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	16 * changed to 8 bit registers with a +1 offset, since track #'s >255 are
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	17 * ignored
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	18 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	19 * NOTE: 512 bytes is reserved as a physical sector buffer. Any reads/
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	20 * writes are done from this buffer to the controller. Copies of the 256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	21 * byte chunk needed are done by a block memory move
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	22 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	23 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	24 ******** DISTO SUPER CONTROLLER II NOTES ********
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	25 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	26 * SCII 0=standard controller 1=Disto Super Controller II
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	27 * SCIIALT 0=Normal I/O register 1=Alternative registers; See below
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	28 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	29 * Disto Super Controller II Registers:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	30 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	31 * $FF74 RW.Dat --- R/W Buffer data #1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	32 * $FF75 mirror of $FF74
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	33 * $FF76 RW.Ctrl --- Write D0 = 0 FDC Write Op #2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	34 * = 1 FDC Read Op #2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	35 * D1 = 0 Normal Mode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	36 * = 1 Buffered I/O Mode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	37 * D2 = 0 Normal NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	38 * = 1 Masked NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	39 * D3 = 0 No FIRQ (Masked)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	40 * = 1 Enabled FIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	41 * Read D7 = FDC INT Status (Inverted)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	42 * $FF77 mirror of $FF76
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	43 * #1: any write to $FF76-$FF77 clears Buffer counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	44 * #2: in buffered mode only
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	45 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	46 * Alternate port is at $FF58-$FF5B in case of hardware conflicts.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	47 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	48 * Edt/Rev YYYY/MM/DD Modified by
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	49 * Comment
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	50 * ------------------------------------------------------------------
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	51 * 11 1993/05/12 ???
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	52 * Special opts for TC9 to slow controller reads and writes TFM's
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	53 * between sector buffers & in drive table init/copies.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	54 * Changed software timing loop (drive spin-up) to F$Sleep for 32 ticks
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	55 * Shrunk (slowed slightly) error returns
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	56 * Added blobstop code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	57 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	58 * 11r1 2003/09/03 Boisy G. Pitre
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	59 * Added code to sense if HW is present or not and return error if not.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	60 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	61 * 1r0 2004/05/20 Boisy G. Pitre
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	62 * Restarted edition due to name change; backported to Level 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	63 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	64 * 2004/06/01 Robert Gault
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	65 * Added code to obtain an SCII driver, at least for the Sleep mode. It
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	66 * would be quite difficult and probably not worth the effort to permit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	67 * selection of both Sleep and IRQ SCII drivers. However, both normal
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	68 * and Alt SCII I/O registers are supported.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	69 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	70 * Cleaned up some errors in the last version of rb1773.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	71 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	72 * 2004/07/11 Robert Gault
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	73 * Corrected the error handling code for read & write to separate SCII errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	74 * from OS-9 errors. Changed drive test from compare #4 to compare #N.Drives to
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	75 * permit up to 6 drives using alternate table.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	76
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	77 nam rb1773
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	78 ttl Western Digital 1773 Disk Controller Driver
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	79
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	80 * These lines needed if assembling with on a Color computer.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	81 SCII set 1 0=not present 1=present
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	82 SCIIALT set 1 0=normal address 1=alternate
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	83 SCIIHACK set 0 * 0=stock model 1=512 byte buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	84 *H6309 set 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	85 *LEVEL set 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	86 * These lines needed if not using latest os9def files.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	87 *TkPerSec set 60
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	88 *DPort set $FF40
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	89
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	90 * This should be changed for NitrOS9 project to "use defsfile"
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	91 IFP1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	92 use defsfile
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	93 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	94
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	95 tylg set Drivr+Objct
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	96 atrv set ReEnt+rev
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	97 rev set $00
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	98 edition set 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	99
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	100 * Configuration Settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	101 N.Drives equ 4 number of drives to support
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	102 TC9 equ 0 Set to 1 for TC9 special slowdowns
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	103 PRECOMP equ 0 Set to 1 to turn on write precompensation
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	104
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	105 * Disto Super Controller defs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	106 IFEQ SCIIALT
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	107 RW.Dat equ $FF74
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	108 RW.Ctrl equ $FF76
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	109 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	110 RW.Dat equ $FF58
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	111 RW.Ctrl equ $FF5A
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	112 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	113
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	114
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	115 * WD-17X3 Definitions
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	116 CtrlReg equ $00 Control register for Tandy controllers; not part of WD
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	117 WD_Cmd equ $08
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	118 WD_Stat equ WD_Cmd
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	119 WD_Trak equ $09
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	120 WD_Sect equ $0A
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	121 WD_Data equ $0B
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	122
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	123 * WD-17X3 Commands
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	124 S$Read equ $80 Read sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	125 S$Format equ $A0 Format track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	126 S$FrcInt equ $D0 Force interrupt
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	127
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	128 * Control Register Definitions
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	129 C_HALT equ %10000000 Halt line to CPU is active when set
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	130 C_SIDSEL equ %01000000 Side select (0 = front side, 1 = back side)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	131 C_DBLDNS equ %00100000 Density (0 = single, 1 = double)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	132 C_WPRCMP equ %00010000 Write precompensation (0 = off, 1 = on)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	133 C_MOTOR equ %00001000 Drive motor (0 = off, 1 = on)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	134 C_DRV2 equ %00000100 Drive 2 selected when set
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	135 C_DRV1 equ %00000010 Drive 1 selected when set
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	136 C_DRV0 equ %00000001 Drive 0 selected when set
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	137
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	138 mod eom,name,tylg,atrv,start,size
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	139
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	140 u0000 rmb DRVBEG+(DRVMEM*N.Drives)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	141 lastdrv rmb 2 Last drive table accessed (ptr)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	142 ctlimg rmb 1 Bit mask for control reg (drive #, side,etc)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	143 u00AA rmb 1 drive change flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	144 sectbuf rmb 2 Ptr to 512 byte sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	145 currside rmb 1 head flag; 0=front 1 = back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	146 u00AE rmb 1 LSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	147 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	148 FBlock rmb 2 block number for format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	149 FTask rmb 1 task number for format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	150 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	151 VIRQPak rmb 2 Vi.Cnt word for VIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	152 u00B3 rmb 2 Vi.Rst word for VIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	153 u00B5 rmb 1 Vi.Stat byte for VIRQ (drive motor timeout)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	154 loglsn rmb 2 OS9's logical sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	155 * Removed next line and added two new ones. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	156 * PCDOS does not ask driver for any info.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	157 * physlsn rmb 2 PCDOS (512 byte sector) #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	158 flag512 rmb 1 PCDOS (512 byte sector) 0=no, 1=yes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	159 flagform rmb 1 SCII format flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	160 size equ .
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	161
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	162 fcb DIR.+SHARE.+PEXEC.+PWRIT.+PREAD.+EXEC.+UPDAT.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	163
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	164 name fcs /rb1773/
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	165 fcb edition
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	166
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	167 VIRQCnt fdb TkPerSec*4 Initial count for VIRQ (4 seconds)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	168
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	169 IRQPkt fcb $00 Normal bits (flip byte)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	170 fcb $01 Bit 1 is interrupt request flag (Mask byte)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	171 fcb 10 Priority byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	172
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	173 * Init
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	174 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	175 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	176 * Y = address of device descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	177 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	178 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	179 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	180 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	181 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	182 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	183 * New code added 09/03/2003 by Boisy G. Pitre
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	184 * Write a pattern to $FF4B and read it back to verify that the hardware
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	185 * does exist.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	186 Init equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	187 * Two new lines for SCII. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	188 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	189 clr RW.Ctrl clear SCII control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	190 clr flagform,u clear SCII format flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	191 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	192 ldx V.PORT,u get Base port address
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	193 lda WD_Data,x get byte at FDC Data register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	194 coma complement it to modify it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	195 sta WD_Data,x write it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	196 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	197 Init2 decb delay a bit...
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	198 bmi Init2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	199 suba WD_Data,x read it back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	200 lbne NoHW if not zero, we didn't read what we wrote
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	201 **
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	202 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	203 clr >D.DskTmr flag drive motor as not running
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	204 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	205 clr <D.MotOn flag drive motor as not running
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	206 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	207 leax WD_Stat,x point to Status/Command register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	208 lda #S$FrcInt "Force Interrupt" command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	209 sta ,x send to FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	210 lbsr FDCDelay time delay for ~ 108 cycles
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	211 lda ,x eat status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	212 ldd #$FF*256+N.Drives 'invalid' value & # of drives
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	213 leax DRVBEG,u point to start of drive tables
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	214 l1 sta ,x DD.TOT MSB to bogus value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	215 sta <V.TRAK,x init current track # to bogus value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	216 leax <DRVMEM,x point to next drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	217 decb done all drives yet?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	218 bne l1 no, init them all
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	219 leax >NMISvc,pc point to NMI service routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	220 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	221 stx <D.NMI install as system NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	222 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	223 stx >D.XNMI+1 NMI jump vector operand
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	224 lda #$7E JMP code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	225 sta >D.XNMI NMI jump vector opcode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	226 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	227 pshs y save device dsc. ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	228 leay >u00B5,u point to Vi.Stat in VIRQ packet
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	229 tfr y,d make it the status register ptr for IRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	230 leay >IRQSvc,pc point to IRQ service routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	231 leax >IRQPkt,pc point to IRQ packet
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	232 os9 F$IRQ install IRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	233 puls y Get back device dsc. ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	234 bcs Return If we can't install IRQ, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	235 ldd #512 Request 512 byte sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	236 pshs u Preserve device mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	237 os9 F$SRqMem Request sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	238 tfr u,x Move ptr to sector buffer to x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	239 puls u Restore device mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	240 bcs Return If error, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	241 stx >sectbuf,u Save ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	242
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	243 * GetStat
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	244 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	245 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	246 * A = function code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	247 * Y = address of path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	248 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	249 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	250 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	251 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	252 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	253 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	254 GetStat clrb no GetStt calls - return, no error, ignore
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	255 Return rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	257 * Term
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	258 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	259 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	260 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	261 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	262 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	263 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	264 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	265 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	266 Term leay >VIRQPak,u Point to VIRQ packet
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	267 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	268 tfr 0,x "remove"
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	269 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	270 ldx #$0000
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	271 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	272 os9 F$VIRQ Remove VIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	273 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	274 tfr 0,x "remove"
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	275 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	276 ldx #$0000
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	277 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	278 leay >IRQSvc,pc point to IRQ service routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	279 os9 F$IRQ Remove IRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	280 pshs u Save device mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	281 ldu >sectbuf,u Get pointer to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	282 ldd #512 Return sector buffer memory
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	283 os9 F$SRtMem
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	284 puls u Restore device mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	285 clr >DPort+CtrlReg shut off drive motors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	286 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	287 clr >D.DskTmr Clear out drive motor timeout flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	288 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	289 clr <D.MotOn Clear out drive motor timeout flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	290 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	291 ex rts return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	292
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	293 * Check if 512 byte sector conversion needed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	294 * Entry: B:X=LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	295 * U=Static mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	296 * Y=Path dsc. ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	297 * Exit: X=New LSN (same as original for 256 byte sectors, 1/2 of original
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	298 * for 512 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	299 * regD changed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	300 Chk512 equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	301 clr flag512,u set to 256 byte sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	302 stx >loglsn,u save OS9 LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	303 lda <PD.TYP,y get device type from path dsc.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	304 anda #%00000100 mask out all but 512 byte sector flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	305 bne Log2Phys 512 byte sectors, go process
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	306 rts RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	307
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	308 * 512 byte sector processing goes here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	309 * regB should be saved and not just cleared at end because there is
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	310 * a subsequent tst for the msb of lsn. The test is pointless if B
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	311 * is changed.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	312 Log2Phys pshs b save MSB of LSN; new RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	313 * Minor inefficiencies here that I have changed, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	314 tfr x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	315 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	316 lsrd
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	317 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	318 lsra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	319 rorb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	320 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	321 tfr d,x move new LSN back to regX
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	322 * New line for stock SCII controller with 256 max no-halt.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	323 inc flag512,u set to 512 byte sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	324 puls b,pc regB will be tested later for >0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	325
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	326 start lbra Init
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	327 bra Read
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	328 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	329 lbra Write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	330 bra GetStat
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	331 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	332 lbra SetStat
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	333 bra Term
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	334 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	335
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	336 * Read
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	337 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	338 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	339 * B = MSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	340 * X = LSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	341 * Y = address of path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	342 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	343 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	344 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	345 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	346 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	347 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	348 Read bsr Chk512 go check for 512 byte sector/adjust if needed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	349 lda #%10010001 error flags (see Disto SCII source)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	350 pshs x preserve sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	351 lbsr ReadWithRetry go read the sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	352 puls x restore sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	353 bcs ex if error, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	354 pshs y,x save path dsc ptr & LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	355 leax ,x LSN0?, ie. tstx
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	356 bne L012D no, go calculate normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	357 puls y,x yes, restore path dsc ptr & LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	358 lda <PD.TYP,y get type from path dsc.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	359 bita #TYP.NSF standard OS-9 format?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	360 beq L00F0 yes, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	361 lbsr MakeDTEntry else make a drive table entry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	362 pshs y,x save path dsc ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	363 bra L012D
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	364
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	365 * LSN0, standard OS-9 format - copy part of LSN0 into drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	366 L00F0 ldx >sectbuf,u Get ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	367 pshs y,x Preserve path dsc. ptr & sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	368 ldy >lastdrv,u Get last drive table accessed ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	369 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	370 ldw #DD.SIZ # bytes to copy from new LSN0 to drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	371 tfm x+,y+ Copy them
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	372 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	373 ldb #DD.SIZ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	374 L00F0Lp lda ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	375 sta ,y+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	376 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	377 bne L00F0Lp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	378 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	379 ldy >lastdrv,u Get drive table ptr back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	380 lda <DD.FMT,y Get format for disk in drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	381 ldy 2,s restore path descriptor pointer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	382 ldb <PD.DNS,y Get path's density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	383 bita #FMT.DNS Disk in drive double density?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	384 beq L0115 No, all drives can read single, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	385 bitb #DNS.MFM Can our path dsc. handle double density?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	386 beq erbtyp No, illegal
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	387 L0115 bita #FMT.TDNS Is new disk 96/135 tpi?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	388 beq L011D No, all drives handle 48 tpi, so skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	389 bitb #DNS.DTD Can path dsc. handle 96/135 tpi?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	390 beq erbtyp No, illegal
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	391 L011D bita #FMT.SIDE Is new disk double sided?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	392 beq L0128 No, all drives handle single sided, we're done
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	393 lda <PD.SID,y Get # sides path dsc. can handle
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	394 suba #2 sides higher or equal to 2?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	395 blo erbtyp Yes, exit with illegal type error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	396 L0128 clrb No error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	397 * LSN's other than 0 come straight here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	398 L012D ldy 2,s Get path dsc. ptr back??
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	399 ldx PD.BUF,y Get path dsc. buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	400 * lda <PD.TYP,y Get path dsc. disk type, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	401 ldy >sectbuf,u Get ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	402 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	403 ldw #256 OS9 sector size (even if physical was 512)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	404 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	405 * anda #%00000100 Mask out all but 512 byte sector flag, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	406 * Next replaces the two lines removed, RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	407 tst flag512,u Is it a 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	408 beq L014B If normal sector, just copy it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	409 ldd >loglsn,u Get OS9's LSN (twice of the 'real' 512 sector)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	410 andb #$01 Mask out all but odd/even sector indicator
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	411 beq L014B Even, use 1st half of 512 byte sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	412 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	413 addr w,y Odd, bump sector buffer ptr to 2nd half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	414 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	415 leay 256,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	416 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	417 L014B equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	418 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	419 tfm y+,x+ Copy from physical sector buffer to PD buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	420 puls pc,y,x restore path dsc & sector buffer ptrs & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	421 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	422 pshs d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	423 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	424 L014BLp lda ,y+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	425 sta ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	426 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	427 bne L014BLp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	428 puls pc,y,x,d restore path dsc & sector buffer ptrs & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	429 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	430
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	431 erbtyp comb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	432 ldb #E$BTyp Error - wrong type error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	433 puls pc,y,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	434
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	435 **********************
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	436 * Read error - retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	437 Retry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	438 bcc ReadWithRetry Normal retry, try reading again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	439 pshs x,d Preserve regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	440 lbsr sktrk0 Seek to track 0 (attempt to recalibrate)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	441 puls x,d Restore regs & try reading again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	442
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	443
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	444 * Read With Retry: Do read with retries
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	445 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	446 * ENTER reg B,X=working lsn on disk
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	447 * Y=path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	448 * U=driver data
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	449 * A=retry sequence mix of read & seek track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	450 * EXIT X,Y,U preserved; D,CC changed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	451 * B=error if any
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	452 * CC=error flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	453 ReadWithRetry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	454 pshs x,d Preserve regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	455 bsr ReadSector Go read sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	456 puls x,d Restore regs (A=retry flags)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	457 lbcc L01D7 No error, return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	458 lsra Shift retry flags
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	459 bne Retry Still more retries allowed, go do them
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	460 * otherwise, final try before we give up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	461 ReadSector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	462 lbsr L02AC Do double-step/precomp etc. if needed, seek
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	463 lbcs L01D7 Error somewhere, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	464 L0176 ldx >sectbuf,u Get physical sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	465 ldb #S$Read Read sector command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	466 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	467 * If SCII not hacked for 512 byte no-halt, must use halt for 512b sectors RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	468 IFEQ SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	469 clra SCII normal mode, normal NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	470 tst flag512,u SCII must use halt mode for 512 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	471 bne L0176B
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	472 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	473 lda #7 SCII read, buffered mode, masked NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	474 bsr L01A1B send commands and wait
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	475 * New lines needed because the SCII has error other than OS-9 errors. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	476 bcs ngood
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	477 * This now becomes a subroutine call. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	478 * lbcs L03AF get the errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	479 lbsr L03AF get the errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	480 bcc good
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	481 ngood rts
1632 93d5b9ff0f4a Fixed 'good' label/pshs y problem. boisy parents: 1631 diff changeset	482
93d5b9ff0f4a Fixed 'good' label/pshs y problem. boisy parents: 1631 diff changeset	483 good pshs y
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	484 IFNE H6309
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	485 ldw #256 set counter
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	486 ldy #RW.DAT source of data
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	487 IFNE SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	488 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	489 beq sc2rlp
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	490 ldw #512 bump up counter to 512 byte sector
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	491 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	492 * Don't use tfm if no halt important else need orcc #$50 for tfm
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	493 * If an interrupt occurs during a tfm transfer, the SCII counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	494 * will update but the tfm will repeat a byte and lose track.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	495 * If orcc #$50 used, then key presses may be lost even with no-halt
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	496 * mode.
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	497 sc2rlp lda ,y read byte from SCII
fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	498 sta ,x+ transfer byte to system buffer
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	499 decw update counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	500 bne sc2rlp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	501 ELSE
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	502 ldy #256
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	503 IFNE SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	504 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	505 beq sc2rlp
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	506 ldy #512
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	507 ENDC
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	508 sc2rlp lda >RW.DAT
fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	509 sta ,x+
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	510 leay -1,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	511 bne sc2rlp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	512 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	513 clrb no errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	514 puls y,pc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	515 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	516
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	517 L0176B bsr L01A1 Send to controller & time delay to let it settle
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	518 *** Next few lines are commented out for blobstop patches
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	519 *L0180 bita >DPort+WD_Stat check status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	520 * bne L0197 eat it & start reading sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	521 * leay -1,y bump timeout timer down
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	522 * bne L0180 keep trying until it reaches 0 or sector read
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	523 * lda >ctlimg,u get current drive settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	524 * ora #C_MOTOR turn drive motor on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	525 * sta >DPort+CtrlReg send to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	526 * puls y,cc restore regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	527 * lbra L03E0 exit with Read Error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	528 *** Blobstop fixes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	529 stb >DPort+CtrlReg send B to control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	530 nop allow HALT to take effect
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	531 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	532 bra L0197 and a bit more time
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	533 * Read loop - exited with NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	534 * Entry: X=ptr to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	535 * B=Control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	536 L0197 lda >DPort+WD_Data get byte from controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	537 sta ,x+ store into sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	538 * stb >DPort+CtrlReg drive info
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	539 nop -- blobstop fix
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	540 bra L0197 Keep reading until sector done
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	541
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	542 L01A1 orcc #IntMasks Shut off IRQ & FIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	543 * No-halt mode must enter here, skipping IRQ shutoff.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	544 L01A1B stb >DPort+WD_Cmd Send command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	545 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	546 sta >RW.Ctrl tell SCII what to do
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	547 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	548 L01A1C ldb #C_DBLDNS+C_MOTOR Double density & motor on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	549 orb >ctlimg,u Merge with current drive settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	550 stb >DPort+CtrlReg Send to control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	551 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	552 tst flagform,u Format uses halt mode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	553 bne s512
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	554 IFEQ SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	555 tst flag512,u SCII uses halt with 512 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	556 beq s256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	557 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	558 bra s256
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	559 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	560 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	561 s512 ldb #C_HALT+C_DBLDNS+C_MOTOR Enable halt, double density & motor on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	562 orb >ctlimg,u Merge that with current drive settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	563 lbra FDCDelay Time delay to wait for command to settle
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	564 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	565 s256 ldb #4 normal mode, NMI masked
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	566 lda #255 time out slices
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	567 pshs a,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	568 SC2tmr1 ldx #1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	569 lbsr Delay sleep or timer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	570 dec ,s count
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	571 beq tmout
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	572 tst >RW.Ctrl check status
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	573 bmi SC2tmr1 loop on not ready
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	574 stb RW.Ctrl clear SCII but don't generate NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	575 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	576 puls a,x,pc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	577 tmout stb RW.Ctrl clear SCII buffer counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	578 lda #$D0 force interrupt
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	579 sta DPort+WD_Cmd
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	580 comb set carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	581 puls a,x,pc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	582 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	583
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	584 * Delay for some number of ticks (1 tick = 1/60 second).
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	585 * For a hard delay, we need to delay for 14833 cycles at .89MHz or
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	586 * 29666 cycles at 1.78MHz
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	587 * Entry: X = number of ticks to delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	588 Delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	589 pshs d [5+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	590 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	591 ldd <D.Proc [6] [5] process pointer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	592 cmpd <D.SysPrc [is it the system?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	593 beq hardloop [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	594 os9 F$Sleep if not system then sleep
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	595 puls d,pc [5+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	596 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	597 hardloop tfr x,d we want X in A,B
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	598 l1@ equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	599 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	600 ldx #1482/2 [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	601 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	602 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	603 ldx #1854 [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	604 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	605 ldx #1482 [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	606 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	607 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	608 l2@ nop [2] [1]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	609 nop [2] [1]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	610 nop [2] [1]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	611 leax -1,x [4+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	612 bne l2@ [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	613 subd #$0001 [4] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	614 bne l1@ [3] [3]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	615 puls d,pc [5+] [4+]
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	616
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	617 * Write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	618 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	619 * B = MSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	620 * X = LSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	621 * Y = address of path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	622 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	623 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	624 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	625 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	626 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	627 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	628 Write lbsr Chk512 go adjust LSN for 512 byte sector if needed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	629 * Next line was lda #%1001001 which was an error RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	630 lda #%10010001 retry flags for I/O errors (see Disto SCII source)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	631 L01C4 pshs x,d preserve LSN, retries
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	632 bsr L01E8 go write the sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	633 puls x,d restore LSN, retries
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	634 bcs L01D8 error writing, go to write retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	635 tst <PD.VFY,y no error, do we want physical verify?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	636 bne L01D6 no, exit without error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	637 lbsr verify go re-read & verify 64 out of 256 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	638 bcs L01D8 error on verify, go to write retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	639 L01D6 clrb no error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	640 L01D7 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	641
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	642 * Write error retry handler
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	643 L01D8 lsra Shift retry flags
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	644 lbeq L03AF Too many retries, exit with error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	645 bcc L01C4 Normal retry, attemp to re-write sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	646 pshs x,d Preserve flags & sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	647 lbsr sktrk0 Seek to track 0 (attempt to recalibrate)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	648 puls x,d Restore flags & sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	649 bra L01C4 Try re-writing now
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	650
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	651 * 512 byte sector write here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	652 L01E8 lbsr L02AC Go do double-step/write precomp if needed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	653 bcs L01D7 Error, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	654 pshs y,d Preserve path dsc. ptr & LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	655 * Since I have modified chk512 the next two lines are replaced. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	656 * lda <PD.TYP,y Get device type
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	657 * anda #%00000100 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	658 tst flag512,u go if 256 byte sectors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	659 beq L020D Not 512 then skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	660 lbsr L0176 Go read the sector in
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	661 ldd >loglsn,u Get OS9 LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	662 andb #$01 Even or odd?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	663 beq L020D Even, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	664 ldx >sectbuf,u Get physical sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	665 leax >$0100,x Point to 2nd half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	666 bra L0211 Copy caller's buffer to 2nd half of sector
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	667
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	668 L020D ldx >sectbuf,u Get physical sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	669
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	670 L0211 ldy PD.BUF,y Get path dsc. buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	671 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	672 ldw #256 Copy write buffer to sector buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	673 tfm y+,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	674 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	675 clrb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	676 L0211Lp lda ,y+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	677 sta ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	678 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	679 bne L0211Lp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	680 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	681 puls y,d Get path dsc. ptr & LSN back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	682 ldx >sectbuf,u Get physical sector buffer ptr again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	683 * See read routine for explanation of SCII code. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	684 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	685 IFEQ SCIIHACK
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	686 clra SCII write, normal mode & NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	687 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	688 bne wr512
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	689 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	690 lda #4 SCII normal mode, masked NMI
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	691 sta RW.Ctrl tell SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	692 pshs y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	693 ldy #RW.Dat Send data to SCII RAM buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	694 IFNE H6309
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	695 ldw #256
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	696 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	697 beq wrbuf
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	698 ldw #512
fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	699 wrbuf lda ,x+
fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	700 sta ,y
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	701 decw
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	702 bne wrbuf
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	703 ELSE
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	704 ldy #256
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	705 tst flag512,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	706 beq wrbuf
1737 fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	707 ldy #512
fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	708 wrbuf lda ,x+
fdb0dde809d2 Boisy, I just had to rebuild my OS-9 system after a problem with a hard drive. One of many files lost was the source for my current cc3disk so I decided to use rb1773.asm. boisy parents: 1632 diff changeset	709 sta >RW.DAT
1631 ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	710 leay -1,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	711 bne wrbuf
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	712 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	713 puls y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	714 ldb #$A0 Write sector command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	715 lda #6 SCII masked NMI, buffered mode, write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	716 * See Read section for explanation of error changes below. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	717 * lbra L01A1B send command to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	718 lbsr L01A1B send command to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	719 bcs wngood SCII error, then go
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	720 lbra L03AF check for OS-9 errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	721 wngood rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	722 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	723 wr512 ldb #S$Format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	724
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	725 * Format track comes here with B=$F0 (write track)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	726 * as does write sector with B=$A0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	727 *WrTrk pshs y,cc Preserve path dsc. ptr & CC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	728 WrTrk lbsr L01A1 Send command to controller (including delay)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	729 *** Commented out for blobstop fixes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	730 *L0229 bita >DPort+WD_Stat Controller done yet?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	731 * bne L0240 Yes, go write sector out
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	732 * leay -$01,y No, bump wait counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	733 * bne L0229 Still more tries, continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	734 * lda >ctlimg,u Get current drive control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	735 * ora #C_MOTOR Drive motor on (but drive select off)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	736 * sta >DPort+CtrlReg Send to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	737 * puls y,cc Restore regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	738 * lbra L03AF Check for errors from status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	739
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	740 *** added blobstop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	741 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	742 lda FBlock+1,u get the block number for format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	743 beq L0230 if not format, don't do anything
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	744 sta >$FFA1 otherwise map the block in
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	745 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	746 L0230 stb >DPort+CtrlReg send data to control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	747 * These lines added to match read routine. Should be better timing. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	748 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	749 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	750 bra L0240 wait a bit for HALT to enable
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	751
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	752 * Write sector routine (Entry: B= drive/side select) (NMI will break out)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	753 * Part of timing change mentioned above. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	754 *L0240 nop --- wait a bit more
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	755 L0240 lda ,x+ Get byte from write buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	756 sta >DPort+WD_Data Save to FDC's data register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	757 * EAT 2 CYCLES: TC9 ONLY (TRY 1 CYCLE AND SEE HOW IT WORKS)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	758 IFEQ TC9-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	759 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	760 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	761 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	762 * See above. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	763 nop
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	764 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	765 * stb >DPort+CtrlReg Set up to read next byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	766 bra L0240 Go read it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	767
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	768 * NMI routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	769 NMISvc leas R$Size,s Eat register stack
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	770 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	771 ldx <D.SysDAT get pointer to system DAT image
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	772 lda 3,x get block number 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	773 sta >$FFA1 map it back into memory
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	774 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	775 andcc #^IntMasks turn IRQ's on again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	776 ldb >DPort+WD_Stat Get status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	777 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	778 clr RW.Ctrl Clear SCII command register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	779 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	780 bitb #%00000100 Did we lose data in the transfer?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	781 lbeq L03B2 Otherwise, check for drive errors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	782 comb -- blobstop error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	783 ldb #E$DevBsy -- device busy
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	784 rts -- and exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	785
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	786 verify pshs x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	787 * Removed unneeded code. Data never sent to PD.BUF anyway so there is
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	788 * no need to redirect the PD.BUF pointer. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	789 * ldx PD.BUF,y Get write buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	790 * pshs x Preserve it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	791 * ldx >sectbuf,u Get sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	792 * stx PD.BUF,y Save as write buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	793 * ldx 4,s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	794 lbsr ReadSector Go read sector we just wrote
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	795 * puls x Get original write buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	796 * stx PD.BUF,y Restore path dsc. version
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	797 bcs L02A3 If error reading, exit with it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	798 ldx PD.BUF,y Get system buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	799 pshs u,y Preserve device mem, path dsc. ptrs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	800 * See change in chk512 routine. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	801 * ldb <PD.TYP,y Get type from path dsc.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	802 ldy >sectbuf,u Get sector buffer ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	803 * andb #%00000100 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	804 tst flag512,u 512 byte sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	805 beq L028D No, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	806 ldd >loglsn,u Get OS9's sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	807 andb #$01 Odd/even sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	808 beq L028D Even; compare first half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	809 leay >$0100,y Odd, compare second half
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	810 L028D tfr x,u Move PD.BUF ptr to U (since cmpx is faster)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	811 clra check all 256 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	812 L028F ldx ,u++ Get 2 bytes from original write buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	813 cmpx ,y++ Same as corresponding bytes in re-read sector?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	814 bne vfybad No, error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	815 inca
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	816 bpl L028F No, continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	817 bra L02A1 carry is clear by virtue of last cmpx
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	818 vfybad comb set carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	819 L02A1 puls u,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	820 L02A3 puls pc,x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	821
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	822 L02A5 pshs a Save Caller's track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	823 ldb <V.TRAK,x Get track # drive is currently on
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	824 bra L02E9 Go save it to controller & continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	825
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	826 L02AC lbsr L0376 Go set up controller for drive, spin motor up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	827 bsr L032B Get track/sector # (A=Trk, B=Sector)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	828 pshs a Save track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	829 lda >currside,u Get side 1/2 flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	830 beq L02C4 Side 1, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	831 lda >ctlimg,u Get control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	832 ora #C_SIDSEL Set side 2 (drive 3) select
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	833 sta >ctlimg,u Save it back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	834 L02C4 lda <PD.TYP,y Get drive type settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	835 bita #%00000010 ??? (Base 0/1 for sector #?)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	836 bne L02CC Skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	837 incb Bump sector # up by 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	838 L02CC stb >DPort+WD_Sect Save into Sector register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	839 ldx >lastdrv,u Get last drive table accessed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	840 ldb <V.TRAK,x Get current track # on device
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	841 lda <DD.FMT,x Get drive format specs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	842 lsra Shift track & bit densities to match PD
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	843 eora <PD.DNS,y Check for differences with path densities
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	844 anda #%00000010 Keep only 48 vs. 96/135 tpi differences
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	845 pshs a Save differences
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	846 lda 1,s Get track # back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	847 tst ,s+ Are tpi's different?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	848 beq L02E9 No, continue normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	849 lsla Yes, multiply track # by 2 ('double-step')
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	850 lslb Multiply current track # by 2 ('double-step')
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	851 L02E9 stb >DPort+WD_Trak Save current track # onto controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	852
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	853 * From here to the line before L0307 is for write precomp, but is not used.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	854 * Unless write precomp is needed, all of this is useless
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	855 * I think most (if not all) drives do NOT need precomp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	856 IFEQ PRECOMP-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	857 ldb #21 Pre-comp track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	858 pshs b Save it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	859 ldb <PD.DNS,y Get current density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	860 andb #%00000010 Just want to check track density
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	861 beq L02F9 48 tpi, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	862 lsl ,s Multiply pre-comp value by 2 ('double-step')
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	863 L02F9 cmpa ,s+ Is track # high enough to warrant precomp?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	864 bls L0307 No, continue normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	865 ldb >ctlimg,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	866 orb #C.WRPCMP Turn on Write precomp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	867 stb >ctlimg,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	868 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	869
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	870 L0307 tst >u00AA,u ??? Get flag (same drive flag?)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	871 bne L0314 no, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	872 ldb ,s get track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	873 cmpb <V.TRAK,x same as current track on this drive?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	874 beq L0321 yes, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	875 L0314 sta >DPort+WD_Data save track # to data register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	876 ldb <PD.STP,y get stepping rate
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	877 andb #%00000011 just keep usable settings (6-30 ms)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	878 eorb #%00011011 set proper bits for controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	879 lbsr L03E4 send command to controller & time delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	880 L0321 puls a get track # back
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	881 sta <V.TRAK,x save as current track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	882 sta >DPort+WD_Trak save to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	883 clrb no error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	884 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	885
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	886 * Entry: B:X LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	887 * Exit: A=Track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	888 * B=Sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	889 * <currside=00 = Head 1 , $FF = Head 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	890 L032B tstb Sector # > 65535?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	891 bne L033F Yes, illegal for floppy
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	892 tfr x,d Move sector # to D
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	893 leax ,x LSN 0? ie. "tstx"
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	894 beq L0371 Yes, exit this routine
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	895 ldx >lastdrv,u Get previous drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	896 cmpd DD.TOT+1,x Within range of drive spec?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	897 blo L0343 Yes, go calculate track/sector #'s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	898 L033F comb Exit with Bad sector # error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	899 ldb #E$Sect
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	900 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	901
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	902 * Calculate track/sector #'s?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	903 * These two sections could be combined into one with a final
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	904 * test of DD.FMT. Then currside can be set and regA can be lsra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	905 * as needed. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	906 L0343 stb >u00AE,u Save LSB of LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	907 clr ,-s Clear track # on stack
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	908 ldb <DD.FMT,x Get drive format
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	909 lsrb Shift out # sides into carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	910 ldb >u00AE,u Get LSB of LSN again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	911 bcc L0367 Single sided drive, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	912 bra L035D Double sided drive, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	913 * Double sided drive handling here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	914 L0355 com >currside,u Odd/even sector track flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	915 bne L035D Odd, so don't bump track # up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	916 inc ,s Bump up track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	917
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	918 * Changed this to more effient code. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	919 *L035D subb DD.TKS,x Subtract # sectors/track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	920 * sbca #$00
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	921 L035D subd DD.SPT,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	922 bcc L0355 Still more sectors left, continue
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	923 bra L036D Wrapped, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	924 * Single sided drive handling here
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	925 L0365 inc ,s Bump track # up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	926
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	927 * See above. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	928 *L0367 subb DD.TKS,x Subtract # sectors/track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	929 * sbca #$00
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	930 L0367 subd DD.SPT,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	931 bcc L0365 Still more, go bump the track up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	932 * Next possible because upper limit is 256 sectors/track. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	933 L036D addb DD.TKS,x Bump sector # back up from negative value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	934 puls a Get the track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	935 L0371 rts A=track #, B=Sector #, <currside=Odd
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	936
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	937 * Drive control register bit mask table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	938 * May want an option here for double sided SDDD disks ex. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	939 * fcb $1 drive0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	940 * fcb $2 drive1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	941 * fcb $41 drive2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	942 * fcb $42 drive3
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	943 * fcb $4 drive4
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	944 * fcb $44 drive5
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	945
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	946 L0372 fcb $01 Drive 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	947 fcb $02 Drive 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	948 fcb $04 Drive 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	949 fcb $40 Drive 3 / Side select
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	950
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	951 * Changes regD; X,Y,U preserved
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	952 L0376 clr >u00AA,u clear drive change flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	953 chkdrv lda <PD.DRV,y Get drive # requested
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	954 * It is possible to have more than 4 drive # so the change below. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	955 * cmpa #4 Drive 0-3?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	956 cmpa #N.Drives Drive 0-6 if alternate table used?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	957 blo L0385 Yes, continue normally
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	958 NoHW comb Illegal drive # error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	959 ldb #E$Unit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	960 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	961
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	962 * Entry: A=drive #, X=LSN (Physical, not OS9 logical if PCDOS disk)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	963 L0385 pshs x,d Save sector #, drive # & B???
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	964 leax >L0372,pc Point to drive bit mask table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	965 ldb a,x Get bit mask for drive # we want
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	966 stb >ctlimg,u Save mask
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	967 leax DRVBEG,u Point to beginning of drive tables
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	968 ldb #DRVMEM Get size of each drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	969 mul Calculate offset to drive table we want
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	970 leax d,x Point to it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	971 cmpx >lastdrv,u Same as Last drive table accessed?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	972 beq L03A6 Yes, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	973 stx >lastdrv,u Save new drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	974 com >u00AA,u Set drive change flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	975 L03A6 clr >currside,u Set side (head) flag to side 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	976 lbsr L04B3 Go set up VIRQ to wait for drive motor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	977 puls pc,x,d Restore sector #,drive #,B & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	978
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	979 L03AF ldb >DPort+WD_Stat Get status register from FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	980 * This line needed when returning to Disk Basic but probably
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	981 * not needed for OS-9. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	982 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	983 clr RW.Ctrl return SCII to halt mode
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	984 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	985 L03B2 bitb #%11111000 any of the error bits set?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	986 beq L03CA No, exit without error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	987 aslb Drive not ready?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	988 bcs L03CC Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	989 aslb Write protect error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	990 bcs L03D0 Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	991 aslb Write fault error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	992 bcs L03D4 Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	993 aslb Sector not found?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	994 bcs L03D8 Yes, use Seek error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	995 aslb CRC error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	996 bcs L03DC Yes, use that error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	997 L03CA clrb No error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	998 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	999
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1000 L03CC ldb #E$NotRdy not ready
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1001 fcb $8C skip 2 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1002
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1003 L03D0 ldb #E$WP write protect
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1004 fcb $8C skip 2 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1005
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1006 L03D4 ldb #E$Write write error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1007 fcb $8C
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1008
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1009 L03D8 ldb #E$Seek seek error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1010 fcb $8C
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1011
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1012 L03DC ldb #E$CRC CRC error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1013 * fcb $8C
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1014
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1015 *L03E0 ldb #E$Read Read error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1016 orcc #Carry set carry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1017 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1018
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1019 L03E4 bsr L0404 Send command to controller & waste some time
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1020 L03E6 ldb >DPort+WD_Stat Check FDC status register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1021 bitb #$01 Is controller still busy?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1022 beq L0403 No, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1023 ldd >VIRQCnt,pc Get initial count value for drive motor speed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1024 std >VIRQPak,u Save it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1025 * Again, I'm trying to match Kevin Darling code. It may not be needed. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1026 pshs x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1027 ldx #1 Sleep remainder of slice
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1028 lbsr Delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1029 puls x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1030 bra L03E6 Wait for controller to finish previous command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1031
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1032 * Send command to FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1033 L03F7 lda #C_MOTOR
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1034 * lda #%00001000 Mask in Drive motor on bit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1035 ora >ctlimg,u Merge in drive/side selects
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1036 sta >DPort+CtrlReg Turn the drive motor on & select drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1037 stb >DPort+WD_Cmd Save command & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1038 L0403 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1039
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1040 L0404 bsr L03F7 Go send command to controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1041
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1042 * This loop has been changed from nested LBSRs to timing loop.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1043 * People with crystal upgrades should modify the loop counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1044 * to get a 58+ us delay time. MINIMUM 58us.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1045 FDCDelay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1046 pshs a 14 cycles, plus 3*loop counter
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1047 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1048 lda #18 (only do about a 100 cycle delay for now)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1049 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1050 lda #29 (only do about a 100 cycle delay for now)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1051 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1052 L0409 deca for total ~63 us delay (123 cycles max.)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1053 bne L0409
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1054 puls a,pc restore register and exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1055
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1056 * SetStat
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1057 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1058 * Entry:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1059 * A = function code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1060 * Y = address of path descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1061 * U = address of device memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1062 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1063 * Exit:
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1064 * CC = carry set on error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1065 * B = error code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1066 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1067 SetStat ldx PD.RGS,y Get caller's register stack ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1068 ldb R$B,x Get function code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1069 cmpb #SS.WTrk Write track?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1070 beq SSWTrk Yes, go do it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1071 cmpb #SS.Reset Restore head to track 0?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1072 lbeq sktrk0 Yes, go do it --- beq
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1073 comb set carry for error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1074 ldb #E$UnkSvc return illegal service request error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1075 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1076
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1077 SSWTrk pshs u,y preserve register stack & descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1078
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1079 * Level 2 Code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1080 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1081
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1082 *--- new code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1083 ldb #1 1 block to allocate
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1084 os9 F$AllRAM allocate some RAM
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1085 lbcs L0489 error out if at all
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1086 leax >FBlock,u point to 'my' DAT image
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1087 std ,x save a copy of the block
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1088 os9 F$ResTsk reserve a task number for the copy
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1089 bcs FError error out
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1090 stb 2,x save temporary task number in FTask,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1091 lslb 2 bytes per entry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1092 ldu <D.TskIPt get task image table pointer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1093 stx b,u save pointer to the task's DAT image
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1094 lsrb get the right number again
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1095 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1096 tfr 0,u destination is address 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1097 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1098 ldu #$0000
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1099 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1100 *--- end new code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1101
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1102 ldx 2,s get pointer to descriptor
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1103 * stu >FBlock,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1104 ldx <D.Proc Get current process ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1105 lda P$Task,x Get task # for current process
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1106 * ldb <D.SysTsk Get system task #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1107 ldy ,s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1108 ldx PD.RGS,y Get register stack ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1109 ldx R$X,x Get ptr to caller's track buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1110 ldy #$1A00 Size of track buffer
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1111 os9 F$Move Copy from caller to temporary task
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1112 bcs L0479 Error copying, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1113 puls u,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1114 pshs u,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1115
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1116 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1117 * End of Level 2 Code
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1118
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1119 lbsr L0376 Go check drive #/wait for it to spin up
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1120 ldx PD.RGS,y Get caller's register stack ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1121 ldb R$Y+1,x Get caller's side/density
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1122 bitb #$01 Check side
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1123 beq L0465 Side 1, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1124 * I think this next line is not needed. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1125 com >currside,u * Why? This is normally used with
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1126 * calculate track. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1127 ldb >ctlimg,u Get current control register settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1128 * orb #%01000000 Mask in side 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1129 orb #C_SIDSEL Mask in side 2
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1130 stb >ctlimg,u Save updated control register
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1131 L0465 lda R$U+1,x Get caller's track #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1132 ldx >lastdrv,u Get current drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1133 lbsr L02A5
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1134 bcs L0489
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1135 ldb #$F0 Write track command
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1136 *---
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1137 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1138 ldx PD.RGS,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1139 ldx R$X,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1140 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1141 ldx #$2000 start writing from block 1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1142 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1143
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1144 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1145 lda #1 normal unbuffered write
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1146 * Next line prevents WrTrk from switching to SCII buffered mode. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1147 sta flagform,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1148 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1149 lbsr WrTrk Go write the track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1150 IFNE SCII
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1151 clr flagform,u permit no-halt mode RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1152 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1153
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1154 IFGT Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1155 L0479 ldu 2,s
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1156 pshs b,cc Preserve error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1157 ldb >FTask,u point to task
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1158 os9 F$RelTsk release the task
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1159 fcb $8C skip 2 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1160
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1161 * format comes here when block allocation passes, but task allocation
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1162 * gives error. So er de-allocate the block.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1163 FError
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1164 pshs b,cc save error code, cc
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1165 ldx >FBlock,u point to block
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1166 ldb #1 1 block to return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1167 os9 F$DelRAM de-allocate image RAM blocks
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1168 clr FBlock+1,u ensure that the block # in FBlock is zero.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1169 puls b,cc Restore error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1170 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1171
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1172 L0489 puls pc,u,y Restore regs & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1173
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1174 * seek the head to track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1175 sktrk0 lbsr chkdrv
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1176 ldx >lastdrv,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1177 clr <$15,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1178 lda #1 was 5 but that causes head banging
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1179 L0497 ldb <PD.STP,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1180 andb #%00000011 Just keep usable settings (6-30 ms)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1181 eorb #%01001011 Set proper bits for controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1182 pshs a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1183 lbsr L03E4
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1184 puls a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1185 deca
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1186 bne L0497
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1187 ldb <PD.STP,y
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1188 andb #%00000011 Just keep usable settings (6-30 ms)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1189 eorb #%00001011 Set proper bits for controller
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1190 lbra L03E4
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1191
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1192 L04B3 pshs y,x,d Preserve regs
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1193 ldd >VIRQCnt,pc Get VIRQ initial count value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1194 std >VIRQPak,u Save it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1195 lda >ctlimg,u ?Get drive?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1196 ora #C_MOTOR Turn drive motor on for that drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1197 * ora #%00001000 Turn drive motor on for that drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1198 sta >DPort+CtrlReg Send drive motor on command to FDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1199 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1200 lda >D.DskTmr Get VIRQ flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1201 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1202 lda <D.MotOn Get VIRQ flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1203 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1204 bmi L04DE Not installed yet, try installing it
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1205 bne L04E0 Drive already up to speed, exit without error
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1206
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1207 * Drive motor speed timing loop (could be F$Sleep call now) (was over .5 sec)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1208 * 32 was not sufficient for one of my drives. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1209 ldx #50 wait for 32 ticks; increased it RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1210 lbsr Delay
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1211
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1212 L04DE bsr InsVIRQ Install VIRQ to wait for drive motors
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1213 L04E0 clrb No error & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1214 puls pc,y,x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1215
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1216 InsVIRQ lda #$01 Flag drive motor is up to speed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1217 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1218 sta >D.DskTmr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1219 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1220 sta <D.MotOn
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1221 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1222 ldx #$0001 Install VIRQ entry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1223 leay >VIRQPak,u Point to packet
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1224 clr Vi.Stat,y Reset Status byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1225 ldd >VIRQCnt,pc Get initial VIRQ count value
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1226 os9 F$VIRQ Install VIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1227 bcc VIRQOut No error, exit
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1228 lda #$80 Flag that VIRQ wasn't installed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1229 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1230 sta >D.DskTmr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1231 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1232 sta <D.MotOn
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1233 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1234 VIRQOut clra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1235 rts
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1236
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1237 * IRQ service routine for VIRQ (drive motor time)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1238 * Entry: U=Ptr to VIRQ memory area
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1239 IRQSvc pshs a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1240 lda <D.DMAReq
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1241 beq L0509
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1242 bsr InsVIRQ
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1243 bra IRQOut
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1244 L0509 sta >DPort+CtrlReg
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1245 * I changed this to a clear. Don't see the point of an AND. RG
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1246 * IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1247 * aim #$FE,>u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1248 * ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1249 * lda u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1250 * anda #$FE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1251 * sta u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1252 * ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1253 * fdb u00B5 --- so changes in data size won't affect anything
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1254 clr u00B5,u
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1255 IFEQ Level-1
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1256 clr >D.DskTmr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1257 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1258 clr <D.MotOn
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1259 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1260 IRQOut puls pc,a
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1261
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1262 * Non-OS9 formatted floppies need a drive table entry constructed
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1263 * by hand since there is no RBF LSN0.
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1264 *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1265 * Entry: X=LSN
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1266 * Y=Path dsc. ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1267 * U=Device mem ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1268 MakeDTEntry
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1269 pshs x Preserve Logical sector #
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1270 ldx >lastdrv,u Get last drive table accessed ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1271 clra
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1272 pshs x,a Save ptr & NUL byte
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1273 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1274 ldw #20 Clear 20 bytes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1275 tfm s,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1276 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1277 ldb #20
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1278 L051ALp clr ,x+
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1279 decb
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1280 bne L051ALp
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1281 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1282 puls x,a Eat NUL & get back drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1283 ldb <PD.CYL+1,y Get # cylinders on drive (ignores high byte)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1284 lda <PD.SID,y Get # sides
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1285 mul Calculate # tracks on drive (1 per head)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1286 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1287 decd Adjust to ignore track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1288 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1289 subd #$0001
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1290 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1291 lda <PD.SCT+1,y Get # sectors/track
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1292 sta DD.TKS,x Save in drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1293 sta <DD.SPT+1,x Save in other copy in drive table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1294 mul Calculate # sectors on drive (minus track 0)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1295 pshs x Preserve drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1296 tfr d,x Move # sectors on drive to X
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1297 lda <PD.T0S+1,y Get # sectors on track 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1298 leax a,x Add that many sectors to total
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1299 lda <PD.TYP,y Get device type settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1300 anda #%00000100 Mask out all but 512 byte sector flag
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1301 beq L0550 Not 512 byte sector, skip ahead
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1302 IFNE H6309
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1303 addr x,x Multiply by 2 (convert to 256 byte OS9 sectors)
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1304 ELSE
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1305 tfr x,d
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1306 leax d,x
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1307 ENDC
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1308 L0550 tfr x,d Move # sectors to D
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1309 puls x Get back drive table ptr
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1310 std DD.TOT+1,x Save # sectors allowed on drive
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1311 lda #UPDAT.+EXEC. Owner's read/write/exec attributes
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1312 sta DD.ATT,x Set attributes for disk
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1313 lda <PD.DNS,y Get density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1314 lsla Shift for DD.FMT
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1315 pshs a Preserve it a sec
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1316 lda <PD.SID,y Get # sides
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1317 deca Adjust to base 0
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1318 ora ,s+ Merge with density settings
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1319 sta <DD.FMT,x Save in device table
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1320 clrb No error?
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1321 puls pc,x Restore original LSN & return
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1322
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1323 emod
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1324 eom equ *
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1325 end
ec6fb5543b22 Robert Gault's modifications for correcting timing errors boisy parents: 1620 diff changeset	1326

Mercurial > hg > Members > kono > nitros9-code

annotate level1/modules/rb1773.asm @ 1737:fdb0dde809d2