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Cleaned up defs files
author boisy
date Thu, 14 Apr 2005 17:10:37 +0000
parents e6e8a44ab20a
children 812b7ef7e21c
comparison
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1803:6b0d1027e4e0 1804:6e5fa42c2fb1
1 IFNE DGNDEFS-1
2
3 DGNDEFS set 1
4
5 ********************************************************************
6 * DgnDefs - Dragon I/O Definitions
1 * 7 *
2 * Deinitions for ports on Dragon 32/64/Alpha. 8 * $Id$
3 * 9 *
4 * 2004/11/16. P.Harvey-Smith. 10 * Edt/Rev YYYY/MM/DD Modified by
5 * Fixed the stupid error I made in the defines below 11 * Comment
6 * that made all the non DPxxxxx defines equal to FF00 !!! 12 * ------------------------------------------------------------------
13 * 2004/11/16 P.Harvey-Smith.
14 * Fixed the stupid error I made in the defines below that made all the
15 * non DPxxxxx defines equal to FF00 !!!
16
17 nam DgnDefs
18 ttl Dragon I/O Definitions
19
20 ********************
21 * CCIO Static Memory
7 * 22 *
8 23 * Definitions for ports on Dragon 32/64/Alpha.
9 IO equ $ff00 ; IO page on Dragon 24 *
25 *
26 IO equ $ff00 IO page on Dragon
10 27
11 * 28 *
12 * Most of these symbols will be defined twice, as some 29 * Most of these symbols will be defined twice, as some
13 * of the Dragon code, sets DP=$FF, and uses direct page 30 * of the Dragon code, sets DP=$FF, and uses direct page
14 * addressing to access the io ports, whilst some of it 31 * addressing to access the io ports, whilst some of it
15 * uses absolute addressing. 32 * uses absolute addressing.
16 * The versions starting DP must be used with DP=$FF. 33 * The versions starting DP must be used with DP=$FF.
17 * 34 *
18 35
19 *Pia 0 and 1 standard on all Dragons. 36 * PIA 0 and 1 standard on all Dragons.
37 DPPIA0DA EQU $00 Side A Data/DDR
38 DPPIA0CRA EQU $01 Side A Control.
39 DPPIA0DB EQU $02 Side B Data/DDR
40 DPPIA0CRB EQU $03 Side B Control.
20 41
21 DPPIA0DA EQU $00 ; Side A Data/DDR 42 PIA0DA EQU DPPIA0DA+IO Side A Data/DDR
22 DPPIA0CRA EQU $01 ; Side A Control. 43 PIA0CRA EQU DPPIA0CRA+IO Side A Control.
23 DPPIA0DB EQU $02 ; Side B Data/DDR 44 PIA0DB EQU DPPIA0DB+IO Side A Data/DDR
24 DPPIA0CRB EQU $03 ; Side B Control. 45 PIA0CRB EQU DPPIA0CRB+IO Side A Control.
25 46
26 PIA0DA EQU DPPIA0DA+IO ; Side A Data/DDR 47 DPPIA1DA EQU $20 Side A Data/DDR
27 PIA0CRA EQU DPPIA0CRA+IO ; Side A Control. 48 DPPIA1CRA EQU $21 Side A Control.
28 PIA0DB EQU DPPIA0DB+IO ; Side A Data/DDR 49 DPPIA1DB EQU $22 Side B Data/DDR
29 PIA0CRB EQU DPPIA0CRB+IO ; Side A Control. 50 DPPIA1CRB EQU $23 Side B Control.
30 51
31 DPPIA1DA EQU $20 ; Side A Data/DDR 52 PIA1DA EQU DPPIA1DA+IO Side A Data/DDR
32 DPPIA1CRA EQU $21 ; Side A Control. 53 PIA1CRA EQU DPPIA1CRA+IO Side A Control.
33 DPPIA1DB EQU $22 ; Side B Data/DDR 54 PIA1DB EQU DPPIA1DB+IO Side A Data/DDR
34 DPPIA1CRB EQU $23 ; Side B Control. 55 PIA1CRB EQU DPPIA1CRB+IO Side A Control.
35 56
36 PIA1DA EQU DPPIA1DA+IO ; Side A Data/DDR 57 * Dragon Alpha has a third PIA at $FF24.
37 PIA1CRA EQU DPPIA1CRA+IO ; Side A Control. 58 DPPIA2DA EQU $24 Side A Data/DDR
38 PIA1DB EQU DPPIA1DB+IO ; Side A Data/DDR 59 DPPIA2CRA EQU $25 Side A Control.
39 PIA1CRB EQU DPPIA1CRB+IO ; Side A Control. 60 DPPIA2DB EQU $26 Side B Data/DDR
61 DPPIA2CRB EQU $27 Side B Control.
40 62
41 * Dragon Alpha has a third PIA at FF24. 63 PIA2DA EQU DPPIA2DA+IO Side A Data/DDR
64 PIA2CRA EQU DPPIA2CRA+IO Side A Control.
65 PIA2DB EQU DPPIA2DB+IO Side A Data/DDR
66 PIA2CRB EQU DPPIA2CRB+IO Side A Control.
42 67
43 DPPIA2DA EQU $24 ; Side A Data/DDR 68 * WD2797 Floppy disk controler, used in Alpha Note registers in reverse order !
44 DPPIA2CRA EQU $25 ; Side A Control. 69 DPCmdRegA EQU $2F command/status
45 DPPIA2DB EQU $26 ; Side B Data/DDR 70 DPTrkRegA EQU $2E Track register
46 DPPIA2CRB EQU $27 ; Side B Control. 71 DPSecRegA EQU $2D Sector register
72 DPDataRegA EQU $2C Data register
47 73
48 PIA2DA EQU DPPIA2DA+IO ; Side A Data/DDR 74 CmdRegA EQU DPCMDREG+IO command/status
49 PIA2CRA EQU DPPIA2CRA+IO ; Side A Control. 75 TrkRegA EQU DPTRKREG+IO Track register
50 PIA2DB EQU DPPIA2DB+IO ; Side A Data/DDR 76 SecRegA EQU DPSECREG+IO Sector register
51 PIA2CRB EQU DPPIA2CRB+IO ; Side A Control. 77 DataRegA EQU DPDATAREG+IO Data register
52 78
53 ;WD2797 Floppy disk controler, used in Alpha Note registers in reverse order ! 79 * Constants for Alpha AY-8912 sound chip, which is used to control
54 DPCmdRegA EQU $2F ; command/status 80 * Drive select and motor on the Alpha
55 DPTrkRegA EQU $2E ; Track register 81 AYIOREG EQU $0E AY-8912, IO Register number.
56 DPSecRegA EQU $2D ; Sector register 82 AYIdle EQU $00 Make AY Idle.
57 DPDataRegA EQU $2C ; Data register 83 AYWriteReg EQU $01 Write AY Register
84 AYReadReg EQU $02 Read AY Register
85 AYREGLatch EQU $03 Latch register into AY
58 86
59 CmdRegA EQU DPCMDREG+IO ; command/status 87 DSMask EQU $03 Drive select mask.
60 TrkRegA EQU DPTRKREG+IO ; Track register 88 MotorMask EQU $04 Motor enable mask
61 SecRegA EQU DPSECREG+IO ; Sector register 89 DDENMask EQU $08 DDEN Mask
62 DataRegA EQU DPDATAREG+IO ; Data register 90 ENPMask EQU $10 Enable Precomp mask
91 NMIMask EQU $20 NMI enable Mask
63 92
64 ; Constants for Alpha AY-8912 sound chip, which is used to control 93 * Dragon 64/Alpha Serial port.
65 ; Drive select and motor on the Alpha 94 DPAciaData EQU $04 ACIA Rx/Tx Register
95 DPAciaStat EQU $05 ACIA status register
96 DPAciaCmd EQU $06 ACIA command register
97 DPAciaCtrl EQU $07 ACIA control register
66 98
67 AYIOREG EQU $0E ; AY-8912, IO Register number. 99 * DragonDos Cartrage IO for WD2797
68 AYIdle EQU $00 ; Make AY Idle. 100 * WD2797 Floppy disk controler, used in DragonDos.
69 AYWriteReg EQU $01 ; Write AY Register 101 DPCmdRegD EQU $40 command/status
70 AYReadReg EQU $02 ; Read AY Register 102 DPTrkRegD EQU $41 Track register
71 AYREGLatch EQU $03 ; Latch register into AY 103 DPSecRegD EQU $42 Sector register
104 DPDataRegD EQU $43 Data register
72 105
73 DSMask EQU $03 ; Drive select mask. 106 CmdRegD EQU DPCMDREG+IO command/status
74 MotorMask EQU $04 ; Motor enable mask 107 TrkRegD EQU DPTRKREG+IO Track register
75 DDENMask EQU $08 ; DDEN Mask 108 SecRegD EQU DPSECREG+IO Sector register
76 ENPMask EQU $10 ; Enable Precomp mask 109 DataRegD EQU DPDATAREG+IO Data register
77 NMIMask EQU $20 ; NMI enable Mask
78 110
79 ; Dragon 64/Alpha Serial port. 111 DPDSKCTL EQU $48 Disk DS/motor control reg
80 DPAciaData EQU $04 ; Acia Rx/Tx Register
81 DPAciaStat EQU $05 ; Acia status register
82 DPAciaCmd EQU $06 ; Acia command register
83 DPAciaCtrl EQU $07 ; Acia control register
84
85 ;DragonDos Cartrage IO for WD2797
86
87 ;WD2797 Floppy disk controler, used in DragonDos.
88 DPCmdRegD EQU $40 ; command/status
89 DPTrkRegD EQU $41 ; Track register
90 DPSecRegD EQU $42 ; Sector register
91 DPDataRegD EQU $43 ; Data register
92
93 CmdRegD EQU DPCMDREG+IO ; command/status
94 TrkRegD EQU DPTRKREG+IO ; Track register
95 SecRegD EQU DPSECREG+IO ; Sector register
96 DataRegD EQU DPDATAREG+IO ; Data register
97
98 DPDSKCTL EQU $48 ; Disk DS/motor control reg
99 DSKCTL EQU DPDSKCTL+IO 112 DSKCTL EQU DPDSKCTL+IO
100 113
101 ; Disk IO bitmasks (DragonDos). 114 * Disk IO bitmasks (DragonDos).
102
103 NMIEnD EQU %00100000 115 NMIEnD EQU %00100000
104 WPCEnD EQU %00010000 116 WPCEnD EQU %00010000
105 SDensEnD EQU %00001000 117 SDensEnD EQU %00001000
106 MotorOnD EQU %00000100 118 MotorOnD EQU %00000100
107 Drive0D EQU %00000000 119 Drive0D EQU %00000000
108 Drive1D EQU %00000001 120 Drive1D EQU %00000001
109 Drive2D EQU %00000010 121 Drive2D EQU %00000010
110 Drive3D EQU %00000011 122 Drive3D EQU %00000011
111 123
112 124
113 ; Disk IO bitmasks (Dragon Alpha). 125 * Disk IO bitmasks (Dragon Alpha).
114 126 NMIEnA EQU %10000000 This is just a guess, but in current code just used as a flag
115 NMIEnA EQU %10000000 ; This is just a guess, but in current code just used as a flag 127 WPCEnA EQU %01000000 According to circuit trace by R.Harding.
116 WPCEnA EQU %01000000 ; Acording to circuit trace by R.Harding. 128 SDensEnA EQU %00000000 DDen is pulled low on the alpha, so always enabled.
117 SDensEnA EQU %00000000 ; DDen is pulled low on the alpha, so always enabled.
118 MotorOnA EQU %00010000 129 MotorOnA EQU %00010000
119 Drive0A EQU %00000001 130 Drive0A EQU %00000001
120 Drive1A EQU %00000010 131 Drive1A EQU %00000010
121 Drive2A EQU %00000100 132 Drive2A EQU %00000100
122 Drive3A EQU %00001000 133 Drive3A EQU %00001000
142 NotRMask EQU %10000000 153 NotRMask EQU %10000000
143 154
144 DensMask EQU %00000001 155 DensMask EQU %00000001
145 T80Mask EQU %00000010 156 T80Mask EQU %00000010
146 157
158 ENDC