Mercurial > hg > Members > kono > nitros9-code
changeset 2770:bfe3de781ddf lwtools-port
Added Arduino dwread/dwwrite changes
| author | Boisy Pitre <boisy.pitre@nuance.com> |
|---|---|
| date | Tue, 22 Jan 2013 19:14:52 -0600 |
| parents | 31cd1f1b4fb0 |
| children | ce3dba57003b |
| files | ChangeLog defs/rbf.d defs/rbsuper.d defs/scsi.d level1/modules/boot_1773.asm level1/modules/boot_scsi.asm level1/modules/dwread.asm level1/modules/dwwrite.asm level1/modules/kernel/krn.asm level1/modules/rbsuper.asm level2/coco3/bootfiles/makefile level2/coco3/makefile level2/coco3/modules/makefile level2/modules/joydrv_6551L.asm level2/modules/krnp4_regdump.asm rules.mak |
| diffstat | 16 files changed, 813 insertions(+), 599 deletions(-) [+] |
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--- a/ChangeLog Mon Dec 10 16:27:38 2012 -0600 +++ b/ChangeLog Tue Jan 22 19:14:52 2013 -0600 @@ -1,5 +1,69 @@ NitrOS-9 V3.2.9: +---------------------------------------------------------- +2012/12/05 Robert Gualt +List of files changed +M ChangeLog +M level1/modules/kernel/krn.asm + +Changed the GetMem rountine for Level1 krn. The routine compared +MaxMem against D.MLIM. This seemed to result in unwarranted loss +of memory and prevented at least one game, Interbank Incident, from running. +The comparison was removed resulting in an increase of available +memory. No problems have been noted. + + +---------------------------------------------------------- +2012/12/05 David Ladd +List of files changed since hg clone on 2012/12/05 +M ChangeLog +M level1/coco/modules/makefile +M rules.mak + +Changes that were made were to supress listing sources to standard +out while compiling project. This change was option "-l" in the rules.mak . + +Change made to level1/coco/modules/makefile was to include adding +dw3_becker.sb and boot_dw3_becker to the level1 build for the CoCo. + +---------------------------------------------------------- +2012/11/09 Gene Heskett +Boisy; +List of files changed since hg clone on 2012/11/03 +M ChangeLog +M ReadMe +M defs/rbf.d +M defs/rbsuper.d +M defs/scsi.d +M level1/atari/cmds/fuji.asm +M level1/coco/modules/makefile +M level1/modules/boot_scsi.asm +M level1/modules/superdesc.asm +M level2/coco3/bootfiles/makefile +M level2/coco3/modules/makefile +M level2/coco3_6309/bootfiles/makefile +M level2/modules/joydrv_6551L.asm +M rules.mak + +AFAICT it will now build bootable .dsk's for all coco's +Running fine on my coco3, and on Roberts Coco3 + +----------------------------------------------------- +With switch to mercurial (Gene Heskett notes, 2012/11/03) + +Level 2 builld, run tested +- joydrv_6551L broken, boot failed, no clue why, code didn't change + Fixed now, works, 2012/11/07 GH + +- All tc^3 drive descriptors broken, over write them in the .dsk's with known + good versions before doing a mb! + +Level 1 atari build +- fuji stuff build failed, assembler syntax error + Fixed, builds but not run tested, I don't have a 6502 or Liber8 fitted atari + +----------------------------------------------------- + Level 2 Only: - joydrv_6551L, joydrv_6551M and joydrv_6552L now have their MPI slot select bytes properly represented and should work.
--- a/defs/rbf.d Mon Dec 10 16:27:38 2012 -0600 +++ b/defs/rbf.d Tue Jan 22 19:14:52 2013 -0600 @@ -273,6 +273,12 @@ DD.NAM RMB 32 Volume name DD.OPT RMB 32 Option area +************************* +* 2012/11/09 Gene Heskett - Some additions for bootlink etc use. + ORG $60 More options from device descriptor +VD.STP RMB 1 This is for the /sh and /ih virtual disks in HDBDOS +VD.OFS RMB 3 This is DT.WPC and DT.OSF combined, might be more + * DD.FMT Bit Definitions - valid only if device is a floppy disk FMT.SIDE EQU %00000001 Single Sided=0, Double Sided=1 FMT.DNS EQU %00000010 Single Density=0, Double Density=1
--- a/defs/rbsuper.d Mon Dec 10 16:27:38 2012 -0600 +++ b/defs/rbsuper.d Tue Jan 22 19:14:52 2013 -0600 @@ -76,7 +76,7 @@ V.LLMem EQU . start of low level driver memory RMB llreserve reserved area... low level driver uses this as it wants V.LLMemSz EQU .-V.LLMem -* Note: we trick rbsuper to so that it thinks its static storage starts at +* Note: we trick rbsuper too so that it thinks its static storage starts at * zero when it really starts beyond DRVBEG+(DRVMEM*DrvCount). RMB UOFFSET V.RBSuper EQU . end of RBSuper's (and ll driver's) memory requirements
--- a/defs/scsi.d Mon Dec 10 16:27:38 2012 -0600 +++ b/defs/scsi.d Tue Jan 22 19:14:52 2013 -0600 @@ -38,6 +38,7 @@ **** Cloud-9 TC^3 Controller Definitions IFNE TC3+SB +SDMPI SET $02 Added 2012\11\05 GH SCSIDATA EQU 0 SCSISTAT EQU 1 SCSISEL EQU 1
--- a/level1/modules/boot_1773.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level1/modules/boot_1773.asm Tue Jan 22 19:14:52 2013 -0600 @@ -85,7 +85,9 @@ * $01 = 12ms * $02 = 20ms * $03 = 30ms + IFNDEF STEP STEP set $00 + ENDC tylg set Systm+Objct atrv set ReEnt+rev
--- a/level1/modules/boot_scsi.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level1/modules/boot_scsi.asm Tue Jan 22 19:14:52 2013 -0600 @@ -40,7 +40,12 @@ * * 4 2008/02/17 Boisy G. Pitre * Message phase code was broken, now fixed and the booter now works. - +* +* 5 2012/11/05-06 Gene Heskett +* SDMPI from defs/scsi.d is being ignored, so boot failed is the message. +* Ded the object to fix that AND the NULL bus address and this code broken. +* WhichDrv is now a zero based decimal value passed in by the makefile via IT.DNS +* Thanks Boisy... NAM Boot TTL SCSI Boot Module @@ -52,7 +57,7 @@ tylg SET Systm+Objct atrv SET ReEnt+rev -rev SET 0 +rev SET 1 edition SET 4 MOD eom,name,tylg,atrv,start,size @@ -108,11 +113,12 @@ * B = error (Carry Set) HWInit clr >$FF40 stop the disk motors - IFNE D4N1+HDII - leax CntlSlot,pcr - lda ,x - sta MPI.Slct - ENDC +* IFNE D4N1+HDII ?????? + IFNE MPI + leax CntlSlot,pcr point at byte with MPI slot in it + lda ,x get it + sta MPI.Slct and set the MPI to us. + ENDC But this was NOT being done. ldd #S$SEEK*256 ldx #0 bsr setup @@ -143,6 +149,10 @@ ENDC rts +* Sooooo, at end of module, the FF64XX, the XX is not a marching bit +* pattern any more. Cool but a huge gotcha needing makefile changes +* all over. And theres too many of them. + scsival FCB $80+1,$80+2,$80+4,$80+8,$80+16,$80+32,$80+64,$80 * SCSI Wake-Up Routine @@ -155,6 +165,10 @@ leax -1,x else count down bne wake and try again if not timed out bra wake4 else branch to timeout +* Aha! New code! so ITDRV goes down one count +* Nice we get a notice. ChangeLog's would be nice +* But are a pain in the ass to maintain. + * Step 2: Put our SCSI ID on the bus wake1 bsr wake3 small delay lda WhichDrv,pcr get SCSI ID @@ -273,12 +287,17 @@ * Fillers to get to $1D0 Pad FILL $39,$1D0-3-1-2-1-* ENDC - -* The default SCSI ID is here +* rev1, add selections for MPI slot and bus address of drive +* 2012\11\05 Gene Heskett +* The default SCSI ID is here, but first do MPI slot + IFEQ MPI-1 CntlSlot FCB SDMPI + ELSE +CntrSlot FCB $FF + ENDC Address FDB SDAddr -WhichDrv FCB 0 - +* So now, this can be a base zero decimal value! +WhichDrv FCB IT.DNS EMOD eom EQU * END
--- a/level1/modules/dwread.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level1/modules/dwread.asm Tue Jan 22 19:14:52 2013 -0600 @@ -1,266 +1,322 @@ -******************************************************* -* -* DWRead -* Receive a response from the DriveWire server. -* Times out if serial port goes idle for more than 1.4 (0.7) seconds. -* Serial data format: 1-8-N-1 -* 4/12/2009 by Darren Atkinson -* -* Entry: -* X = starting address where data is to be stored -* Y = number of bytes expected -* -* Exit: -* CC = carry set on framing error, Z set if all bytes received -* X = starting address of data received -* Y = checksum -* U is preserved. All accumulators are clobbered -* - - - IFNE BECKER - -* NOTE: There is no timeout currently on here... -DWRead pshs cc,d,x,u - leau ,x - ldx #$0000 - orcc #IntMasks -loop@ ldb $FF41 - bitb #$02 - beq loop@ - ldb $FF42 - stb ,u+ - abx - leay -1,y - bne loop@ - - tfr x,y - puls cc - andcc #^Carry - orcc #Zero - puls d,x,u,pc - - ELSE - IFNE BAUD38400 -******************************************************* -* 38400 bps using 6809 code and timimg -******************************************************* - -DWRead clra ; clear Carry (no framing error) - deca ; clear Z flag, A = timeout msb ($ff) - tfr cc,b - pshs u,x,dp,b,a ; preserve registers, push timeout msb - orcc #$50 ; mask interrupts - tfr a,dp ; set direct page to $FFxx - setdp $ff - leau ,x ; U = storage ptr - ldx #0 ; initialize checksum - adda #2 ; A = $01 (serial in mask), set Carry - -* Wait for a start bit or timeout -rx0010 bcc rxExit ; exit if timeout expired - ldb #$ff ; init timeout lsb -rx0020 bita <BBIN ; check for start bit - beq rxByte ; branch if start bit detected - subb #1 ; decrement timeout lsb - bita <BBIN - beq rxByte - bcc rx0020 ; loop until timeout lsb rolls under - bita <BBIN - beq rxByte - addb ,s ; B = timeout msb - 1 - bita <BBIN - beq rxByte - stb ,s ; store decremented timeout msb - bita <BBIN - bne rx0010 ; loop if still no start bit - -* Read a byte -rxByte leay ,-y ; decrement request count - ldd #$ff80 ; A = timeout msb, B = shift counter - sta ,s ; reset timeout msb for next byte -rx0030 exg a,a - nop - lda <BBIN ; read data bit - lsra ; shift into carry - rorb ; rotate into byte accumulator - lda #$01 ; prep stop bit mask - bcc rx0030 ; loop until all 8 bits read - - stb ,u+ ; store received byte to memory - abx ; update checksum - ldb #$ff ; set timeout lsb for next byte - anda <BBIN ; read stop bit - beq rxExit ; exit if framing error - leay ,y ; test request count - bne rx0020 ; loop if another byte wanted - lda #$03 ; setup to return SUCCESS - -* Clean up, set status and return -rxExit leas 1,s ; remove timeout msb from stack - inca ; A = status to be returned in C and Z - ora ,s ; place status information into the.. - sta ,s ; ..C and Z bits of the preserved CC - leay ,x ; return checksum in Y - puls cc,dp,x,u,pc ; restore registers and return - setdp $00 - - - ELSE - IFNE H6309-1 -******************************************************* -* 57600 (115200) bps using 6809 code and timimg -******************************************************* - -DWRead clra ; clear Carry (no framing error) - deca ; clear Z flag, A = timeout msb ($ff) - tfr cc,b - pshs u,x,dp,b,a ; preserve registers, push timeout msb - orcc #$50 ; mask interrupts - tfr a,dp ; set direct page to $FFxx - setdp $ff - leau ,x ; U = storage ptr - ldx #0 ; initialize checksum - lda #$01 ; A = serial in mask - bra rx0030 ; go wait for start bit - -* Read a byte -rxByte leau 1,u ; bump storage ptr - leay ,-y ; decrement request count - lda <BBIN ; read bit 0 - lsra ; move bit 0 into Carry - ldd #$ff20 ; A = timeout msb, B = shift counter - sta ,s ; reset timeout msb for next byte - rorb ; rotate bit 0 into byte accumulator -rx0010 lda <BBIN ; read bit (d1, d3, d5) - lsra - rorb - bita 1,s ; 5 cycle delay - bcs rx0020 ; exit loop after reading bit 5 - lda <BBIN ; read bit (d2, d4) - lsra - rorb - leau ,u - bra rx0010 - -rx0020 lda <BBIN ; read bit 6 - lsra - rorb - leay ,y ; test request count - beq rx0050 ; branch if final byte of request - lda <BBIN ; read bit 7 - lsra - rorb ; byte is now complete - stb -1,u ; store received byte to memory - abx ; update checksum - lda <BBIN ; read stop bit - anda #$01 ; mask out other bits - beq rxExit ; exit if framing error - -* Wait for a start bit or timeout -rx0030 bita <BBIN ; check for start bit - beq rxByte ; branch if start bit detected - bita <BBIN ; again - beq rxByte - ldb #$ff ; init timeout lsb -rx0040 bita <BBIN - beq rxByte - subb #1 ; decrement timeout lsb - bita <BBIN - beq rxByte - bcc rx0040 ; loop until timeout lsb rolls under - bita <BBIN - beq rxByte - addb ,s ; B = timeout msb - 1 - bita <BBIN - beq rxByte - stb ,s ; store decremented timeout msb - bita <BBIN - beq rxByte - bcs rx0030 ; loop if timeout hasn't expired - bra rxExit ; exit due to timeout - -rx0050 lda <BBIN ; read bit 7 of final byte - lsra - rorb ; byte is now complete - stb -1,u ; store received byte to memory - abx ; calculate final checksum - lda <BBIN ; read stop bit - anda #$01 ; mask out other bits - ora #$02 ; return SUCCESS if no framing error - -* Clean up, set status and return -rxExit leas 1,s ; remove timeout msb from stack - inca ; A = status to be returned in C and Z - ora ,s ; place status information into the.. - sta ,s ; ..C and Z bits of the preserved CC - leay ,x ; return checksum in Y - puls cc,dp,x,u,pc ; restore registers and return - setdp $00 - - - ELSE -******************************************************* -* 57600 (115200) bps using 6309 native mode -******************************************************* - -DWRead clrb ; clear Carry (no framing error) - decb ; clear Z flag, B = $FF - pshs u,x,dp,cc ; preserve registers - orcc #$50 ; mask interrupts -* ldmd #1 ; requires 6309 native mode - tfr b,dp ; set direct page to $FFxx - setdp $ff - leay -1,y ; adjust request count - leau ,x ; U = storage ptr - tfr 0,x ; initialize checksum - lda #$01 ; A = serial in mask - bra rx0030 ; go wait for start bit - -* Read a byte -rxByte sexw ; 4 cycle delay - ldw #$006a ; shift counter and timing flags - clra ; clear carry so next will branch -rx0010 bcc rx0020 ; branch if even bit number (15 cycles) - nop ; extra (16th) cycle -rx0020 lda <BBIN ; read bit - lsra ; move bit into carry - rorb ; rotate bit into byte accumulator - lda #0 ; prep A for 8th data bit - lsrw ; bump shift count, timing bit to carry - bne rx0010 ; loop until 7th data bit has been read - incw ; W = 1 for subtraction from Y - inca ; A = 1 for reading bit 7 - anda <BBIN ; read bit 7 - lsra ; move bit 7 into carry, A = 0 - rorb ; byte is now complete - stb ,u+ ; store received byte to memory - abx ; update checksum - subr w,y ; decrement request count - inca ; A = 1 for reading stop bit - anda <BBIN ; read stop bit - bls rxExit ; exit if completed or framing error - -* Wait for a start bit or timeout -rx0030 clrw ; initialize timeout counter -rx0040 bita <BBIN ; check for start bit - beq rxByte ; branch if start bit detected - addw #1 ; bump timeout counter - bita <BBIN - beq rxByte - bcc rx0040 ; loop until timeout rolls over - lda #$03 ; setup to return TIMEOUT status - -* Clean up, set status and return -rxExit beq rx0050 ; branch if framing error - eora #$02 ; toggle SUCCESS flag -rx0050 inca ; A = status to be returned in C and Z - ora ,s ; place status information into the.. - sta ,s ; ..C and Z bits of the preserved CC - leay ,x ; return checksum in Y - puls cc,dp,x,u,pc ; restore registers and return - setdp $00 - - ENDC - ENDC - ENDC +******************************************************* +* +* DWRead +* Receive a response from the DriveWire server. +* Times out if serial port goes idle for more than 1.4 (0.7) seconds. +* Serial data format: 1-8-N-1 +* 4/12/2009 by Darren Atkinson +* +* Entry: +* X = starting address where data is to be stored +* Y = number of bytes expected +* +* Exit: +* CC = carry set on framing error, Z set if all bytes received +* X = starting address of data received +* Y = checksum +* U is preserved. All accumulators are clobbered +* + + IFNE ARDUINO +* Note: this is an optimistic routine. It presumes that the server will always be there, and +* has NO timeout fallback. It is also very short and quick. +DWRead clra ; clear Carry (no framing error) + pshs u,x,cc ; preserve registers + leau ,x + ldx #$0000 +loop@ tst $FF51 ; check for CA1 bit (1=Arduino has byte ready) + bpl loop@ ; loop if not set + ldb $FF50 ; clear CA1 bit in status register + stb ,u+ ; save off acquired byte + abx ; update checksum + leay ,-y + bne loop@ + + leay ,x ; return checksum in Y + puls cc,x,u,pc ; restore registers and return + + ELSE + + IFNE JMCPBCK +* NOTE: There is no timeout currently on here... +DWRead clra ; clear Carry (no framing error) + deca ; clear Z flag, A = timeout msb ($ff) + tfr cc,b + pshs u,x,dp,b,a ; preserve registers, push timeout msb + leau ,x + ldx #$0000 + orcc #IntMasks +loop@ ldb $FF4C + bitb #$02 + beq loop@ + ldb $FF44 + stb ,u+ + abx + leay ,-y + bne loop@ + + tfr x,y + ldb #0 + lda #3 + leas 1,s ; remove timeout msb from stack + inca ; A = status to be returned in C and Z + ora ,s ; place status information into the.. + sta ,s ; ..C and Z bits of the preserved CC + leay ,x ; return checksum in Y + puls cc,dp,x,u,pc ; restore registers and return + ELSE + IFNE BECKER +* NOTE: There is no timeout currently on here... +DWRead clra ; clear Carry (no framing error) + deca ; clear Z flag, A = timeout msb ($ff) + tfr cc,b + pshs u,x,dp,b,a ; preserve registers, push timeout msb + leau ,x + ldx #$0000 + orcc #IntMasks +loop@ ldb $FF41 + bitb #$02 + beq loop@ + ldb $FF42 + stb ,u+ + abx + leay ,-y + bne loop@ + + tfr x,y + ldb #0 + lda #3 + leas 1,s ; remove timeout msb from stack + inca ; A = status to be returned in C and Z + ora ,s ; place status information into the.. + sta ,s ; ..C and Z bits of the preserved CC + leay ,x ; return checksum in Y + puls cc,dp,x,u,pc ; restore registers and return + ENDC + ENDC + + IFEQ BECKER+JMCPBCK+ARDUINO + IFNE BAUD38400 +******************************************************* +* 38400 bps using 6809 code and timimg +******************************************************* + +DWRead clra ; clear Carry (no framing error) + deca ; clear Z flag, A = timeout msb ($ff) + tfr cc,b + pshs u,x,dp,b,a ; preserve registers, push timeout msb + orcc #$50 ; mask interrupts + tfr a,dp ; set direct page to $FFxx + setdp $ff + leau ,x ; U = storage ptr + ldx #0 ; initialize checksum + adda #2 ; A = $01 (serial in mask), set Carry + +* Wait for a start bit or timeout +rx0010 bcc rxExit ; exit if timeout expired + ldb #$ff ; init timeout lsb +rx0020 bita <BBIN ; check for start bit + beq rxByte ; branch if start bit detected + subb #1 ; decrement timeout lsb + bita <BBIN + beq rxByte + bcc rx0020 ; loop until timeout lsb rolls under + bita <BBIN + beq rxByte + addb ,s ; B = timeout msb - 1 + bita <BBIN + beq rxByte + stb ,s ; store decremented timeout msb + bita <BBIN + bne rx0010 ; loop if still no start bit + +* Read a byte +rxByte leay ,-y ; decrement request count + ldd #$ff80 ; A = timeout msb, B = shift counter + sta ,s ; reset timeout msb for next byte +rx0030 exg a,a + nop + lda <BBIN ; read data bit + lsra ; shift into carry + rorb ; rotate into byte accumulator + lda #$01 ; prep stop bit mask + bcc rx0030 ; loop until all 8 bits read + + stb ,u+ ; store received byte to memory + abx ; update checksum + ldb #$ff ; set timeout lsb for next byte + anda <BBIN ; read stop bit + beq rxExit ; exit if framing error + leay ,y ; test request count + bne rx0020 ; loop if another byte wanted + lda #$03 ; setup to return SUCCESS + +* Clean up, set status and return +rxExit leas 1,s ; remove timeout msb from stack + inca ; A = status to be returned in C and Z + ora ,s ; place status information into the.. + sta ,s ; ..C and Z bits of the preserved CC + leay ,x ; return checksum in Y + puls cc,dp,x,u,pc ; restore registers and return + setdp $00 + + + ELSE + IFEQ H6309 +******************************************************* +* 57600 (115200) bps using 6809 code and timimg +******************************************************* + +DWRead clra ; clear Carry (no framing error) + deca ; clear Z flag, A = timeout msb ($ff) + tfr cc,b + pshs u,x,dp,b,a ; preserve registers, push timeout msb + orcc #$50 ; mask interrupts + tfr a,dp ; set direct page to $FFxx + setdp $ff + leau ,x ; U = storage ptr + ldx #0 ; initialize checksum + lda #$01 ; A = serial in mask + bra rx0030 ; go wait for start bit + +* Read a byte +rxByte leau 1,u ; bump storage ptr + leay ,-y ; decrement request count + lda <BBIN ; read bit 0 + lsra ; move bit 0 into Carry + ldd #$ff20 ; A = timeout msb, B = shift counter + sta ,s ; reset timeout msb for next byte + rorb ; rotate bit 0 into byte accumulator +rx0010 lda <BBIN ; read bit (d1, d3, d5) + lsra + rorb + bita 1,s ; 5 cycle delay + bcs rx0020 ; exit loop after reading bit 5 + lda <BBIN ; read bit (d2, d4) + lsra + rorb + leau ,u + bra rx0010 + +rx0020 lda <BBIN ; read bit 6 + lsra + rorb + leay ,y ; test request count + beq rx0050 ; branch if final byte of request + lda <BBIN ; read bit 7 + lsra + rorb ; byte is now complete + stb -1,u ; store received byte to memory + abx ; update checksum + lda <BBIN ; read stop bit + anda #$01 ; mask out other bits + beq rxExit ; exit if framing error + +* Wait for a start bit or timeout +rx0030 bita <BBIN ; check for start bit + beq rxByte ; branch if start bit detected + bita <BBIN ; again + beq rxByte + ldb #$ff ; init timeout lsb +rx0040 bita <BBIN + beq rxByte + subb #1 ; decrement timeout lsb + bita <BBIN + beq rxByte + bcc rx0040 ; loop until timeout lsb rolls under + bita <BBIN + beq rxByte + addb ,s ; B = timeout msb - 1 + bita <BBIN + beq rxByte + stb ,s ; store decremented timeout msb + bita <BBIN + beq rxByte + bcs rx0030 ; loop if timeout hasn't expired + bra rxExit ; exit due to timeout + +rx0050 lda <BBIN ; read bit 7 of final byte + lsra + rorb ; byte is now complete + stb -1,u ; store received byte to memory + abx ; calculate final checksum + lda <BBIN ; read stop bit + anda #$01 ; mask out other bits + ora #$02 ; return SUCCESS if no framing error + +* Clean up, set status and return +rxExit leas 1,s ; remove timeout msb from stack + inca ; A = status to be returned in C and Z + ora ,s ; place status information into the.. + sta ,s ; ..C and Z bits of the preserved CC + leay ,x ; return checksum in Y + puls cc,dp,x,u,pc ; restore registers and return + setdp $00 + + + ELSE +******************************************************* +* 57600 (115200) bps using 6309 native mode +******************************************************* + +DWRead clrb ; clear Carry (no framing error) + decb ; clear Z flag, B = $FF + pshs u,x,dp,cc ; preserve registers + orcc #$50 ; mask interrupts +* ldmd #1 ; requires 6309 native mode + tfr b,dp ; set direct page to $FFxx + setdp $ff + leay -1,y ; adjust request count + leau ,x ; U = storage ptr + tfr 0,x ; initialize checksum + lda #$01 ; A = serial in mask + bra rx0030 ; go wait for start bit + +* Read a byte +rxByte sexw ; 4 cycle delay + ldw #$006a ; shift counter and timing flags + clra ; clear carry so next will branch +rx0010 bcc rx0020 ; branch if even bit number (15 cycles) + nop ; extra (16th) cycle +rx0020 lda <BBIN ; read bit + lsra ; move bit into carry + rorb ; rotate bit into byte accumulator + lda #0 ; prep A for 8th data bit + lsrw ; bump shift count, timing bit to carry + bne rx0010 ; loop until 7th data bit has been read + incw ; W = 1 for subtraction from Y + inca ; A = 1 for reading bit 7 + anda <BBIN ; read bit 7 + lsra ; move bit 7 into carry, A = 0 + rorb ; byte is now complete + stb ,u+ ; store received byte to memory + abx ; update checksum + subr w,y ; decrement request count + inca ; A = 1 for reading stop bit + anda <BBIN ; read stop bit + bls rxExit ; exit if completed or framing error + +* Wait for a start bit or timeout +rx0030 clrw ; initialize timeout counter +rx0040 bita <BBIN ; check for start bit + beq rxByte ; branch if start bit detected + addw #1 ; bump timeout counter + bita <BBIN + beq rxByte + bcc rx0040 ; loop until timeout rolls over + lda #$03 ; setup to return TIMEOUT status + +* Clean up, set status and return +rxExit beq rx0050 ; branch if framing error + eora #$02 ; toggle SUCCESS flag +rx0050 inca ; A = status to be returned in C and Z + ora ,s ; place status information into the.. + sta ,s ; ..C and Z bits of the preserved CC + leay ,x ; return checksum in Y + puls cc,dp,x,u,pc ; restore registers and return + setdp $00 + + ENDC + ENDC + ENDC + ENDC
--- a/level1/modules/dwwrite.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level1/modules/dwwrite.asm Tue Jan 22 19:14:52 2013 -0600 @@ -1,194 +1,180 @@ -******************************************************* -* -* DWWrite -* Send a packet to the DriveWire server. -* Serial data format: 1-8-N-1 -* 4/12/2009 by Darren Atkinson -* -* Entry: -* X = starting address of data to send -* Y = number of bytes to send -* -* Exit: -* X = address of last byte sent + 1 -* Y = 0 -* All others preserved -* - - - IFNE BECKER - -DWWrite pshs d,cc ; preserve registers - orcc #$50 ; mask interrupts -; ldu #BBOUT ; point U to bit banger out register -; lda 3,u ; read PIA 1-B control register -; anda #$f7 ; clear sound enable bit -; sta 3,u ; disable sound output -; fcb $8c ; skip next instruction - -txByte - lda ,x+ - sta $FF42 - leay -1,y ; decrement byte counter - bne txByte ; loop if more to send - - puls cc,d,pc ; restore registers and return - - - ELSE - IFNE H6309-1 -******************************************************* -* 57600 (115200) bps using 6809 code and timimg -******************************************************* - -DWWrite pshs dp,d,cc ; preserve registers - orcc #$50 ; mask interrupts - ldd #$04ff ; A = loop counter, B = $ff - tfr b,dp ; set direct page to $FFxx - setdp $ff - ldb <$ff23 ; read PIA 1-B control register - andb #$f7 ; clear sound enable bit - stb <$ff23 ; disable sound output - fcb $8c ; skip next instruction - -txByte stb <BBOUT ; send stop bit - ldb ,x+ ; get a byte to transmit - nop - lslb ; left rotate the byte two positions.. - rolb ; ..placing a zero (start bit) in bit 1 -tx0020 stb <BBOUT ; send bit (start bit, d1, d3, d5) - rorb ; move next bit into position - exg a,a - nop - stb <BBOUT ; send bit (d0, d2, d4, d6) - rorb ; move next bit into position - leau ,u - deca ; decrement loop counter - bne tx0020 ; loop until 7th data bit has been sent - - stb <BBOUT ; send bit 7 - ldd #$0402 ; A = loop counter, B = MARK value - leay ,-y ; decrement byte counter - bne txByte ; loop if more to send - - stb <BBOUT ; leave bit banger output at MARK - puls cc,d,dp,pc ; restore registers and return - setdp $00 - - ELSE - IFNE BAUD38400 -******************************************************* -* 38400 bps using 6809 code and timimg -******************************************************* - -DWWrite pshs u,d,cc ; preserve registers - orcc #$50 ; mask interrupts - ldu #BBOUT ; point U to bit banger out register - lda 3,u ; read PIA 1-B control register - anda #$f7 ; clear sound enable bit - sta 3,u ; disable sound output - fcb $8c ; skip next instruction - -txByte stb ,--u ; send stop bit - leau ,u+ - lda #8 ; counter for start bit and 7 data bits - ldb ,x+ ; get a byte to transmit - lslb ; left rotate the byte two positions.. - rolb ; ..placing a zero (start bit) in bit 1 -tx0010 stb ,u++ ; send bit - tst ,--u - rorb ; move next bit into position - deca ; decrement loop counter - bne tx0010 ; loop until 7th data bit has been sent - leau ,u - stb ,u ; send bit 7 - lda ,u++ - ldb #$02 ; value for stop bit (MARK) - leay -1,y ; decrement byte counter - bne txByte ; loop if more to send - - stb ,--u ; leave bit banger output at MARK - puls cc,d,u,pc ; restore registers and return - - - ELSE - IFNE H6309-1 -******************************************************* -* 57600 (115200) bps using 6809 code and timimg -******************************************************* - -DWWrite pshs dp,d,cc ; preserve registers - orcc #$50 ; mask interrupts - ldd #$04ff ; A = loop counter, B = $ff - tfr b,dp ; set direct page to $FFxx - setdp $ff - ldb <$ff23 ; read PIA 1-B control register - andb #$f7 ; clear sound enable bit - stb <$ff23 ; disable sound output - fcb $8c ; skip next instruction - -txByte stb <BBOUT ; send stop bit - ldb ,x+ ; get a byte to transmit - nop - lslb ; left rotate the byte two positions.. - rolb ; ..placing a zero (start bit) in bit 1 -tx0020 stb <BBOUT ; send bit (start bit, d1, d3, d5) - rorb ; move next bit into position - exg a,a - nop - stb <BBOUT ; send bit (d0, d2, d4, d6) - rorb ; move next bit into position - leau ,u - deca ; decrement loop counter - bne tx0020 ; loop until 7th data bit has been sent - - stb <BBOUT ; send bit 7 - ldd #$0402 ; A = loop counter, B = MARK value - leay ,-y ; decrement byte counter - bne txByte ; loop if more to send - - stb <BBOUT ; leave bit banger output at MARK - puls cc,d,dp,pc ; restore registers and return - setdp $00 - - - ELSE -******************************************************* -* 57600 (115200) bps using 6309 native mode -******************************************************* - -DWWrite pshs u,d,cc ; preserve registers - orcc #$50 ; mask interrupts -* ldmd #1 ; requires 6309 native mode - ldu #BBOUT+1 ; point U to bit banger out register +1 - aim #$f7,2,u ; disable sound output - lda #8 ; counter for start bit and 7 data bits - fcb $8c ; skip next instruction - -txByte stb -1,u ; send stop bit -tx0010 ldb ,x+ ; get a byte to transmit - lslb ; left rotate the byte two positions.. - rolb ; ..placing a zero (start bit) in bit 1 - bra tx0030 - -tx0020 bita #1 ; even or odd bit number ? - beq tx0040 ; branch if even (15 cycles) -tx0030 nop ; extra (16th) cycle -tx0040 stb -1,u ; send bit - rorb ; move next bit into position - deca ; decrement loop counter - bne tx0020 ; loop until 7th data bit has been sent - leau ,u+ - stb -1,u ; send bit 7 - ldd #$0802 ; A = loop counter, B = MARK value - leay -1,y ; decrement byte counter - bne txByte ; loop if more to send - - stb -1,u ; final stop bit - puls cc,d,u,pc ; restore registers and return - - - ENDC - ENDC - ENDC - ENDC +******************************************************* +* +* DWWrite +* Send a packet to the DriveWire server. +* Serial data format: 1-8-N-1 +* 4/12/2009 by Darren Atkinson +* +* Entry: +* X = starting address of data to send +* Y = number of bytes to send +* +* Exit: +* X = address of last byte sent + 1 +* Y = 0 +* All others preserved +* + + + IFNE ARDUINO +DWWrite pshs a ; preserve registers +txByte + lda ,x+ ; get byte from buffer + sta $FF52 ; put it to PIA +loop@ tst $FF53 ; check status register + bpl loop@ ; until CB1 is set by Arduino, continue looping + tst $FF52 ; clear CB1 in status register + leay -1,y ; decrement byte counter + bne txByte ; loop if more to send + + puls a,pc ; restore registers and return + + ELSE + + IFNE JMCPBCK +DWWrite pshs d,cc ; preserve registers + orcc #$50 ; mask interrupts +txByte + lda ,x+ + sta $FF44 + leay -1,y ; decrement byte counter + bne txByte ; loop if more to send + + puls cc,d,pc ; restore registers and return + + ELSE + IFNE BECKER +DWWrite pshs d,cc ; preserve registers + orcc #$50 ; mask interrupts +; ldu #BBOUT ; point U to bit banger out register +; lda 3,u ; read PIA 1-B control register +; anda #$f7 ; clear sound enable bit +; sta 3,u ; disable sound output +; fcb $8c ; skip next instruction + +txByte + lda ,x+ + sta $FF42 + leay -1,y ; decrement byte counter + bne txByte ; loop if more to send + + puls cc,d,pc ; restore registers and return + ENDC + ENDC + + IFEQ BECKER+JMCPBCK+ARDUINO + IFEQ BAUD38400+H6309 +******************************************************* +* 57600 (115200) bps using 6809 code and timimg +******************************************************* + +DWWrite pshs dp,d,cc ; preserve registers + orcc #$50 ; mask interrupts + ldd #$04ff ; A = loop counter, B = $ff + tfr b,dp ; set direct page to $FFxx + setdp $ff + ldb <$ff23 ; read PIA 1-B control register + andb #$f7 ; clear sound enable bit + stb <$ff23 ; disable sound output + fcb $8c ; skip next instruction + +txByte stb <BBOUT ; send stop bit + ldb ,x+ ; get a byte to transmit + nop + lslb ; left rotate the byte two positions.. + rolb ; ..placing a zero (start bit) in bit 1 +tx0020 stb <BBOUT ; send bit (start bit, d1, d3, d5) + rorb ; move next bit into position + exg a,a + nop + stb <BBOUT ; send bit (d0, d2, d4, d6) + rorb ; move next bit into position + leau ,u + deca ; decrement loop counter + bne tx0020 ; loop until 7th data bit has been sent + + stb <BBOUT ; send bit 7 + ldd #$0402 ; A = loop counter, B = MARK value + leay ,-y ; decrement byte counter + bne txByte ; loop if more to send + + stb <BBOUT ; leave bit banger output at MARK + puls cc,d,dp,pc ; restore registers and return + setdp $00 + ELSE + + IFNE BAUD38400 +******************************************************* +* 38400 bps using 6809 code and timimg +******************************************************* + +DWWrite pshs u,d,cc ; preserve registers + orcc #$50 ; mask interrupts + ldu #BBOUT ; point U to bit banger out register + lda 3,u ; read PIA 1-B control register + anda #$f7 ; clear sound enable bit + sta 3,u ; disable sound output + fcb $8c ; skip next instruction + +txByte stb ,--u ; send stop bit + leau ,u+ + lda #8 ; counter for start bit and 7 data bits + ldb ,x+ ; get a byte to transmit + lslb ; left rotate the byte two positions.. + rolb ; ..placing a zero (start bit) in bit 1 +tx0010 stb ,u++ ; send bit + tst ,--u + rorb ; move next bit into position + deca ; decrement loop counter + bne tx0010 ; loop until 7th data bit has been sent + leau ,u + stb ,u ; send bit 7 + lda ,u++ + ldb #$02 ; value for stop bit (MARK) + leay -1,y ; decrement byte counter + bne txByte ; loop if more to send + + stb ,--u ; leave bit banger output at MARK + puls cc,d,u,pc ; restore registers and return + + + ELSE +******************************************************* +* 57600 (115200) bps using 6309 native mode +******************************************************* + +DWWrite pshs u,d,cc ; preserve registers + orcc #$50 ; mask interrupts +* ldmd #1 ; requires 6309 native mode + ldu #BBOUT+1 ; point U to bit banger out register +1 + aim #$f7,2,u ; disable sound output + lda #8 ; counter for start bit and 7 data bits + fcb $8c ; skip next instruction + +txByte stb -1,u ; send stop bit +tx0010 ldb ,x+ ; get a byte to transmit + lslb ; left rotate the byte two positions.. + rolb ; ..placing a zero (start bit) in bit 1 + bra tx0030 + +tx0020 bita #1 ; even or odd bit number ? + beq tx0040 ; branch if even (15 cycles) +tx0030 nop ; extra (16th) cycle +tx0040 stb -1,u ; send bit + rorb ; move next bit into position + deca ; decrement loop counter + bne tx0020 ; loop until 7th data bit has been sent + leau ,u+ + stb -1,u ; send bit 7 + ldd #$0802 ; A = loop counter, B = MARK value + leay -1,y ; decrement byte counter + bne txByte ; loop if more to send + + stb -1,u ; final stop bit + puls cc,d,u,pc ; restore registers and return + + + ENDC + ENDC + ENDC + ENDC
--- a/level1/modules/kernel/krn.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level1/modules/kernel/krn.asm Tue Jan 22 19:14:52 2013 -0600 @@ -252,11 +252,13 @@ bita #CRCOn CRC on? beq GetMem branch if not (already cleared earlier) inc <D.CRC else turn on CRC checking -GetMem ldd MaxMem+1,u - clrb - cmpd <D.MLIM - bcc L0158 - std <D.MLIM +*GetMem ldd MaxMem+1,u I don't think this exists for Level1 RG +* clrb +* cmpd <D.MLIM starts as $EE00 +* bra L0158 +* std <D.MLIM +GetMem equ * Initially I tried GetMem clra +* that is redundant. See last line. RG L0158 ldx <D.FMBM IFNE atari * In the Atari, memory $0000-$08FF is used by the system
--- a/level1/modules/rbsuper.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level1/modules/rbsuper.asm Tue Jan 22 19:14:52 2013 -0600 @@ -21,7 +21,9 @@ * H6309 - if set, assembles for 6309 * USECS - if set, uses critical section code (slows down driver) * HDBDOS - if set, adds code to handle HDB-DOS partitions -* +* And somewhere this flag has been lost GH 2012/11/13 +* Only found when I trashed my systems vdisks +HDBDOS set 1 * Edt/Rev YYYY/MM/DD Modified by * Comment * ------------------------------------------------------------------
--- a/level2/coco3/bootfiles/makefile Mon Dec 10 16:27:38 2012 -0600 +++ b/level2/coco3/bootfiles/makefile Tue Jan 22 19:14:52 2013 -0600 @@ -10,6 +10,7 @@ KERNEL_1773 = $(MD)/rel_80 $(MD)/boot_1773_6ms $(MD)/krn KERNEL_1773_50HZ = $(MD)/rel_80_50hz $(MD)/boot_1773_6ms $(MD)/krn KERNEL_DW = $(MD)/rel_80 $(MD)/boot_dw $(MD)/krn +KERNEL_ARDUINO = $(MD)/rel_80 $(MD)/boot_dw_arduino $(MD)/krn KERNEL_BECKER = $(MD)/rel_80 $(MD)/boot_dw_becker $(MD)/krn FLOPPY_40D = $(MD)/rb1773.dr $(MD)/d0_40d.dd $(MD)/d1_40d.dd $(MD)/d2_40d.dd @@ -41,6 +42,8 @@ $(MD)/w5.dw $(MD)/w6.dw $(MD)/w7.dw RBDW = $(MD)/rbdw.dr $(MD)/dwio.sb \ $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd +RBDWARDUINO = $(MD)/rbdw.dr $(MD)/dwio_arduino.sb \ + $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd RBDWBECKER = $(MD)/rbdw.dr $(MD)/dwio_becker.sb \ $(MD)/x1.dd $(MD)/x2.dd $(MD)/x3.dd SCDWV_NET = $(MD)/n_scdwv.dd $(MD)/n1_scdwv.dd $(MD)/n2_scdwv.dd \ @@ -73,6 +76,21 @@ $(PIPE) \ $(CLOCK60HZBECKER) +# NitrOS-9 disk bootfile to allow booting from DriveWire server +# on an Arduino and CoCoPort +BOOTFILE_ARDUINO = $(MD)/krnp2 $(MD)/ioman $(MD)/init \ + $(MD)/rbf.mn \ + $(RBDWARDUINO) \ + $(FLOPPY_40D) \ + $(MD)/ddx0.dd \ + $(MD)/scf.mn \ + $(VTIO_COGRF_80) \ + $(MD)/scdwv.dr \ + $(SCDWV_NET) \ + $(SCDWP) \ + $(PIPE) \ + $(CLOCK60HZ) + # NitrOS-9 disk bootfile to allow booting from DriveWire 3 server BOOTFILE_DW = $(MD)/krnp2 $(MD)/ioman $(MD)/init \ $(MD)/rbf.mn \ @@ -146,8 +164,8 @@ $(PIPE) \ $(CLOCK50HZ) -BOOTFILES = bootfile_40d bootfile_40d_50hz bootfile_80d bootfile_80d_50hz bootfile_dw bootfile_dw_headless bootfile_becker -KERNELS = kernel_1773 kernel_1773_50hz kernel_dw kernel_becker +BOOTFILES = bootfile_40d bootfile_40d_50hz bootfile_80d bootfile_80d_50hz bootfile_dw bootfile_dw_headless bootfile_becker bootfile_arduino +KERNELS = kernel_1773 kernel_1773_50hz kernel_dw kernel_becker kernel_arduino ALLOBJS = $(BOOTFILES) $(KERNELS) @@ -157,6 +175,9 @@ bootfile_becker: $(BOOTFILE_BECKER) $(DEPENDS) $(MERGE) $(BOOTFILE_BECKER)>$@ +bootfile_arduino: $(BOOTFILE_ARDUINO) $(DEPENDS) + $(MERGE) $(BOOTFILE_ARDUINO)>$@ + bootfile_40d: $(BOOTFILE_40D) $(DEPENDS) $(MERGE) $(BOOTFILE_40D)>$@ @@ -179,6 +200,9 @@ kernel_becker: $(KERNEL_BECKER) $(DEPENDS) $(MERGE) $(KERNEL_BECKER)>$@ +kernel_arduino: $(KERNEL_ARDUINO) $(DEPENDS) + $(MERGE) $(KERNEL_ARDUINO)>$@ + kernel_1773: $(KERNEL_1773) $(DEPENDS) $(MERGE) $(KERNEL_1773)>$@
--- a/level2/coco3/makefile Mon Dec 10 16:27:38 2012 -0600 +++ b/level2/coco3/makefile Tue Jan 22 19:14:52 2013 -0600 @@ -10,6 +10,7 @@ DISTRONAME = nos9$(CPU)l$(LEVEL) DISTROVER = $(DISTRONAME)$(NITROS9VER)$(PORT) BOOTFILE_BECKER = bootfiles/bootfile_becker +BOOTFILE_ARDUINO = bootfiles/bootfile_arduino BOOTFILE_DW = bootfiles/bootfile_dw BOOTFILE_DWHEADLESS = bootfiles/bootfile_dw_headless BOOTFILE_40D = bootfiles/bootfile_40d @@ -17,6 +18,7 @@ BOOTFILE_40D_50HZ = bootfiles/bootfile_40d_50hz BOOTFILE_80D_50HZ = bootfiles/bootfile_80d_50hz KERNELFILE_BECKER = bootfiles/kernel_becker +KERNELFILE_ARDUINO = bootfiles/kernel_arduino KERNELFILE = bootfiles/kernel_1773 KERNELFILE_50HZ = bootfiles/kernel_1773_50hz KERNELFILE_DW = bootfiles/kernel_dw @@ -52,6 +54,7 @@ DSK360K_1_50HZ = $(DISTROVER)_40d_1_50hz.dsk LDSK360K_1_50HZ = $(DISTRONAME)_40d_1_50hz.dsk DSKBECKER = $(DISTROVER)_becker.dsk +DSKARDUINO = $(DISTROVER)_arduino.dsk DSK360K_2 = $(DISTROVER)_40d_2.dsk LDSK360K_2 = $(DISTRONAME)_40d_2.dsk DSK720K = $(DISTROVER)_80d.dsk @@ -59,10 +62,11 @@ DSK720K_50HZ = $(DISTROVER)_80d_50hz.dsk LDSK720K_50HZ = $(DISTRONAME)_80d_50hz.dsk LDSKBECKER = $(DISTRONAME)_80d_becker.dsk +LDSKARDUINO = $(DISTRONAME)_arduino.dsk TESTDSK = test.dsk -DSKS = $(DSKDW) $(DSK360K_1) $(DSK360K_1_50HZ) $(DSK360K_2) $(DSK720K) $(DSK720K_50HZ) $(DSKDW) $(DSKDWHEADLESS) $(DSKBECKER) -LDSKS = $(LDSKDW) $(LDSK360K_1) $(LDSK360K_1_50HZ) $(LDSK360K_2) $(LDSK720K) $(LDSK720K_50HZ) $(LDSKDW) $(LDSKDWHEADLESS) $(LDSKBECKER) +DSKS = $(DSKDW) $(DSK360K_1) $(DSK360K_1_50HZ) $(DSK360K_2) $(DSK720K) $(DSK720K_50HZ) $(DSKDW) $(DSKDWHEADLESS) $(DSKBECKER) $(DSKARDUINO) +LDSKS = $(LDSKDW) $(LDSK360K_1) $(LDSK360K_1_50HZ) $(LDSK360K_2) $(LDSK720K) $(LDSK720K_50HZ) $(LDSKDW) $(LDSKDWHEADLESS) $(LDSKBECKER) $(LDSKARDUINO) # Make all components all: @@ -146,6 +150,60 @@ $(RM) $(LDSKBECKER) $(SOFTLINK) $@ $(LDSKBECKER) +$(DSKARDUINO): + -$(RM) $@ + $(OS9FORMAT_DW) -q $@ -n"NitrOS-9/$(CPU) Level 2" + $(OS9GEN) $@ -b=$(BOOTFILE_ARDUINO) -t=$(KERNELFILE_ARDUINO) + $(MAKDIR) $@,CMDS + $(MAKDIR) $@,SYS + $(MAKDIR) $@,DEFS + $(CP) modules/$(CCBKRN) $@,$(CCBKRN) + $(CP) modules/$(SYSGO) $@,sysgo + $(OS9ATTR_EXEC) $@,sysgo + $(CD) cmds; $(CP) $(CMDS_DW) ../$@,CMDS + $(foreach file, $(CMDS_DW), $(OS9ATTR_EXEC) $@,CMDS/$(file);) + $(CD) sys; $(CP) $(SYSBIN) ../$@,SYS + $(foreach file, $(SYSBIN), $(OS9ATTR_TEXT) $@,SYS/$(file);) + $(CD) sys; $(CPL) $(SYSTEXT) ../$@,SYS + $(foreach file, $(SYSTEXT), $(OS9ATTR_TEXT) $@,SYS/$(file);) + $(CD) defs; $(CPL) $(DEFS) ../$@,DEFS + $(foreach file, $(DEFS), $(OS9ATTR_TEXT) $@,DEFS/$(file);) + $(CPL) $(STARTUP_DW) $@,startup + $(OS9ATTR_TEXT) $@,startup + $(MAKDIR) $@,NITROS9 + $(MAKDIR) $@,NITROS9/$(DISTRO) + $(MAKDIR) $@,NITROS9/$(DISTRO)/CMDS + $(CD) cmds; $(CP) $(MODULECMDS) ../$@,NITROS9/$(DISTRO)/CMDS + $(foreach file, $(MODULECMDS), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/CMDS/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/BOOTTRACK + $(CD) modules; $(CP) $(BOOTTRACK) ../$@,NITROS9/$(DISTRO)/MODULES/BOOTTRACK + $(foreach file, $(BOOTTRACK), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/BOOTTRACK/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/KERNEL + $(CD) modules; $(CP) $(KERNEL) ../$@,NITROS9/$(DISTRO)/MODULES/KERNEL + $(foreach file, $(KERNEL), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/KERNEL/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/SYSMODS + $(CD) modules; $(CP) $(SYSMODS) ../$@,NITROS9/$(DISTRO)/MODULES/SYSMODS + $(foreach file, $(SYSMODS), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/SYSMODS/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/CLOCKS + $(CD) modules; $(CP) $(CLOCKS) ../$@,NITROS9/$(DISTRO)/MODULES/CLOCKS + $(foreach file, $(CLOCKS), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/CLOCKS/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/RBF + $(CD) modules; $(CP) $(RBF) ../$@,NITROS9/$(DISTRO)/MODULES/RBF + $(foreach file, $(RBF), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/RBF/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/SCF + $(CD) modules; $(CP) $(SCF) ../$@,NITROS9/$(DISTRO)/MODULES/SCF + $(foreach file, $(SCF), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/SCF/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/MODULES/PIPE + $(CD) modules; $(CP) $(PIPE) ../$@,NITROS9/$(DISTRO)/MODULES/PIPE + $(foreach file, $(PIPE), $(OS9ATTR_EXEC) $@,NITROS9/$(DISTRO)/MODULES/PIPE/$(file);) + $(MAKDIR) $@,NITROS9/$(DISTRO)/BOOTLISTS + $(CD) bootlists; $(CPL) *.bl ../$@,NITROS9/$(DISTRO)/BOOTLISTS + $(MAKDIR) $@,NITROS9/$(DISTRO)/SCRIPTS + $(CD) scripts; $(CPL) mb* ../$@,NITROS9/$(DISTRO)/SCRIPTS + $(RM) $(LDSKARDUINO) + $(SOFTLINK) $@ $(LDSKARDUINO) + $(DSKDW): -$(RM) $@ $(OS9FORMAT_DW) -q $@ -n"NitrOS-9/$(CPU) Level 2"
--- a/level2/coco3/modules/makefile Mon Dec 10 16:27:38 2012 -0600 +++ b/level2/coco3/modules/makefile Tue Jan 22 19:14:52 2013 -0600 @@ -22,7 +22,7 @@ TPB = $(3RDPARTY)/booters BOOTERS = boot_1773_6ms boot_1773_30ms \ - boot_burke boot_rampak boot_wd1002 boot_dw boot_dw_becker \ + boot_burke boot_rampak boot_wd1002 boot_dw boot_dw_becker boot_dw_arduino \ boot_tc3 boot_ide boot_rom BOOTTRACK = rel_32 rel_40 rel_80 rel_32_50hz rel_40_50hz rel_80_50hz $(BOOTERS) krn KERNEL = krnp2 krnp3_perr krnp4_regdump @@ -33,7 +33,7 @@ clock2_jvemu clock2_messemu clock2_dw clock2_dw_becker RBF = rbf.mn \ - rbdw.dr dwio.sb dwio_becker.sb \ + rbdw.dr dwio.sb dwio_becker.sb dwio_arduino.sb \ rb1773.dr rb1773_scii_ff74.dr rb1773_scii_ff58.dr \ d0_35s.dd d1_35s.dd d2_35s.dd d3_35s.dd \ d0_40d.dd d1_40d.dd d2_40d.dd d0_80d.dd \ @@ -110,6 +110,14 @@ dwio_becker.sb: dwio.asm $(AS) $< $(ASOUT)$@ $(AFLAGS) -DBECKER=1 +# DriveWire Becker Booter +boot_dw_arduino: boot_dw.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DARDUINO=1 + +# DriveWire Arduino Submodule +dwio_arduino.sb: dwio.asm + $(AS) $< $(ASOUT)$@ $(AFLAGS) -DARDUINO=1 + # CoGrf/CoVDG Modules cogrf.io: cowin.asm $(AS) $< $(ASOUT)$@ $(AFLAGS) -DCoGrf=1
--- a/level2/modules/joydrv_6551L.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level2/modules/joydrv_6551L.asm Tue Jan 22 19:14:52 2013 -0600 @@ -47,10 +47,20 @@ * but detects 4th byte from a Logitek mouse & switches modes * till next reboot. * Also no 6309 optimizations yet. Version A maybe? Not yet. + +* damn this editor, it lets me open a file, do an hours worth of +* hacking on a file I don't own, but the sumbitch doesn't tell +* me until I go to save an hours work! So I have to re-invent +* this wheel every damned time. + +* Now we start on version 13 +* GH 2012/11/01 trying to make this work again, it died with +* the conversion to a mercurial repo on srcfrg. + * one problem has been the narrow list format, Boisy advises: opt w132 nam JoyDrv - ttl Joystick Driver for 6551/Logitech Mouse + ttl Joystick Driver for 6551/Logitech or M$ Mouse * Disassembled 98/09/09 09:22:44 by Disasm v1.6 (C) 1988 by RML @@ -60,15 +70,15 @@ endc * l51.defs - something else to check against google et all * l51.defs has been modified, this needs the new version -* set this to get some debugging in the boot trace -DEBUG = 1 +* set this to get some debugging and a lockup in the boot trace +DEBUG = 0 tylg set Systm+Objct atrv set ReEnt+rev -rev set $02 -edition set 11 +rev set $01 +edition set 13 * set this to where your rs-232 pack is plugged in MPISlot set $00 front slot for mine - +* the $FF6C is the mouses port address, change to suit your system. mod eom,name,tylg,atrv,start,$FF6C name fcs /JoyDrv/ @@ -82,10 +92,9 @@ lbra SSMsXY lbra SSJoyBtn -* This code is not being -* used, but save it so I -* don't have to reinvent -* this wheel later +* This code is not being used as we have SSMsXY, but save it so I +* don't have to reinvent this wheel later but no clue why +* so it will die in next Edition 14 if not sooner. GH. *SSJoyXY pshs x,b,a * ldx #PIA0Base * lda <$23,x @@ -140,7 +149,7 @@ IRQPckt equ * Pkt.Flip fcb Stat.Flp D.Poll flip byte=$00 Pkt.Mask fcb Stat.RxF is correct - fcb $01 priority=low + fcb $01 priority=low, mouse is pretty slow *** * JoyDrv Initialization. @@ -153,53 +162,54 @@ * ERROR OUTPUT: CC = Carry set * B = error code * first, suspend all interrupts -Init pshs cc save regs we alter +Init pshs cc save regs we alter, stack -1 orcc #IntMasks mask IRQs while disabling ACIA - bsr InitPIAs - bsr InitGIME - bsr ClrACIA reset, gobble up trash data in ACIA - bcc ClrBuf which will also install IRQSvs - puls cc else error - lbsr Term - comb - ldb #E$PrcAbt - rts and return error + bsr InitPIAs stack still -1 + bsr InitGIME stack still -1 +* we should see a bunch of stuff here, ending in 'D' + lbsr ClrACIA reset, clear trash data in ACIA, stack -1 on rtn + bcc SetBuf which will also install IRQSvs stack -1 yet + bcc Alldone else stack still -1 + lbra Term it won't come back! +Alldone puls cc,pc and return clean -************************************* +*****SetBuf************************** * Btn.Cntr,u offset 0 has room for 3 bits of incoming * byte counter, 3 bits of button status. * Buffer, offset 2-3 is the combined first 3 bytes * of the incoming XY data * CrntXpos, offset 4-5 is current (0-HResMaxX) xpos * CrntYpos, offset 6-7 is current (0 to HResMaxY*2) ypos - -ClrBuf ldd #$0007 clear the buffer -ClrBuf1 sta b,u A=$00 - decb decr counter - bne ClrBuf1 was a bpl, so 1st byte wasn't cleared -* Now init the buffer to real data - clrb reset to $00, s/b $00 here anyway. - sta Btn.Cntr,u set up Rx data sync, no button(s) pressed - std CrntXPos,u set up X position at left screen edge - ldd #HResMaxY*2 =$017E, 382 decimal? Odd value, check - std CrntYPos,u set up Y position at top screen edge - lda #'M preset M$ mouse - sta Buffer,u - +SetBuf lda #$00 + ldb #'M set Buffer,u to M$ mode + std Btn.Cntr,u set up Rx data sync, no button(s) pressed + clrb + std CrntXPos,u set up X position at left screen edge + ldd #HResMaxY*2 =$017E, 382 decimal? Odd value, check + std CrntYPos,u set up Y position at top screen edge * Now we should be ready for live IRQ's InstIRQ ldd M$Mem,pcr get base hardware address addd #StatReg status register address + pshs x,y leax IRQPckt,pcr leay IRQSvc,pcr os9 F$IRQ install the IRQSvs routine + puls x,y lbcs InitErr go with cc on stack! - puls cc get rid of the push - rts +* Now, enable rx Rx IRQ's + ldx M$Mem,pcr but first clean out any instant IRQ's + lda DataReg,x dump it to the bitbucket + lda StatReg,x likewise, clear any irq's pending +* Now, enable the IRQ's + ldd #(TIC.RTS!Cmd.DTR)*256+(DB.7!Ctl.RClk!BR.01200) enable rx IRQs + std CmdReg,x and enable Rx IRQ's + puls cc Fix the stack! + rts so stack = 0 now * BUG FIX: InitExit is now here... was TermExit... InitExit puls pc,cc recover original regs, return... -* clear the PIA's for this +* clear the PIA's for this, stack is -3 on entry InitPIAs lda >PIA1Base+3 get PIA CART* input control register anda #$FC clear PIA CART* control bits sta >PIA1Base+3 disable PIA CART* FIRQs @@ -210,14 +220,14 @@ jsr <D.BtBug puls a,b,x,u,y,cc,dp endc - rts + rts stack still -1 InitGIME lda #$01 GIME CART* IRQ enable ora <D.IRQER mask in current GIME IRQ enables sta <D.IRQER save GIME CART* IRQ enable shadow register sta >IrqEnR enable GIME CART* IRQs lda SlotSlct,pcr mpi slot of mouse - bmi ClrACIA + bmi ClrACIA if no mpi sta >MPI.Slct ifeq DEBUG-1 pshs a,b,x,u,y,cc,dp @@ -225,77 +235,51 @@ jsr <D.BtBug puls a,b,x,u,y,cc,dp endc - rts + rts And stack still -1 ClrACIA ldx M$Mem,pcr get base hardware address again lda #$10 sta StatReg,x reset again -* major foobar. These mice are 7n2 mice, not 8n1 -* Fixed 25/06/2008 GH - ldd #(TIC.RTS!Cmd.DTR)*256+(DB.7!Ctl.RClk!BR.01200) [D]=command:control +* start it up with rx IRQs disabled + ldd #(TIC.RTS!Cmd.DTR!Cmd.RxIE)*256+(DB.7!Ctl.RClk!BR.01200) [D]=command:control std CmdReg,x set command and control registers * do instant reads for trash collection * and clear status of Stat.RxF bits -* read it 16 times so its settled! - ldb #$10 -flshinit lda DataReg,x - lda StatReg,x +* read it 32 times so its settled! +* and get rid of this headache + ldb #$02 +flshinit lda StatReg,x +* look at everything + ifeq DEBUG-1 + pshs a,b,x,u,y,cc,dp + jsr <D.BtBug lets see what its doing + puls a,b,x,u,y,cc,dp + endc + lda DataReg,x + ifeq DEBUG-1 + pshs a,b,x,u,y,cc,dp + jsr <D.BtBug lets see what its doing + puls a,b,x,u,y,cc,dp + endc decb bne flshinit - -* that kills some of the 14 milliseconds -* to the mouses first response byte -* now, lets see what mouse we have -* my mouse does a $7F as it powers up as first byte - bsr GetByte GetByte shows _ char - bsr GetByte GetByte shows M char, but its a logitek - bsr GetByte GetByte shows 3 char, ?number of buttons? -* it will either get the first 3 bytes, or timeout -* and ATM, a timeout will lock the boot to display it -GotByte rts - -********************************* -* Entry : x pointing at hardware -* Mangles: a,b -* Returns: char in A -* Error : cc set, err code in B -* scans acia for a byte of data -* Switch this out also +* looks like 2x is enough to clear things, its P3P3P3 till end. +* Fall thru to KilTim -GetByte pshs y - ldy #$01A0 set timeout to fail -GetByte1 leay -1,y - beq GByteFai - clra kill some time -Dly1 deca - bne Dly1 - lda StatReg,x look for byte - anda Pkt.Mask,pcr - tsta Stat.RxF - beq GetByte1 - lda DataReg,x -* show byte on boot screen - pshs a,b,x,u,y,cc,dp - jsr <D.BtBug - puls a,b,x,u,y,cc,dp - puls y - clrb in case cc set - rts +* this should allow the acia to overflow etc as the power/signin bytes come in +* but the Rx irq is disabled. +* We need at least 14 milliseconds plus 3 bytes at 1200 baud, +* which is 25 ms or about 40 milliseconds total. +KilTim pshs y stack -3 + ldb #$03 a small time delay +rloadlp ldy #$1FFF ditto, +dodelay leay -1,y + bne dodelay + decb + clra + puls y stack -1 + rts Return success regardless, stack -1 -GByteFai puls y - clrb clear carry - ifeq DEBUG-1 -* show failure on boot screen a 't' - pshs a,b,x,u,y,cc,dp - lda #'T indicate timeout - jsr <D.BtBug - puls a,b,x,u,y,cc,dp - endc -GBytFail comb set carry - ldb #E$PrcAbt -* lock up boot to show failure -lettgsho bra lettgsho -* rts *** Only used by failed Init routine! * JoyDrv Termination. @@ -318,18 +302,18 @@ leay IRQSvc,pcr os9 F$IRQ - ifeq DEBUG-1 +* ifeq DEBUG-1 pshs a,b,x,y,u,cc,dp lda #'j failed jsr <D.BtBug puls a,b,x,y,u,cc,dp - endc +* endc TermExit puls cc clear stack letssee bra letssee lock it with failed data on screen -* comb -* ldb #E$PrcAbt -* rts + comb + ldb #E$PrcAbt + rts ************************* * This code only good for tandy * Joysticks. Why here? @@ -365,7 +349,7 @@ * A, X, and U registers may be altered * * ERROR OUTPUT: none -* AND HERE IS WHERE THE BUTTON DATA IS LOST! + SSMsBtn pshs cc orcc #IntMasks mask interrupts lda Btn.Cntr,u
--- a/level2/modules/krnp4_regdump.asm Mon Dec 10 16:27:38 2012 -0600 +++ b/level2/modules/krnp4_regdump.asm Tue Jan 22 19:14:52 2013 -0600 @@ -22,6 +22,8 @@ * ------------------------------------------------------------------ * 1 1989/02/?? Ron Lammardo * Started. +* 2 2012/11/22 Gene Heskett +* Remove final cr to save screen space nam krnp4 ttl User Register Dump System Call for NitrOS9 Level 2 @@ -102,7 +104,7 @@ ldd P$SP,y get users stack address addd #R$Size add on for registers which were saved bsr reg000 dump register S - lbsr reg060 send a <CR> +* lbsr reg060 send a <CR> leas 60,s restore stack pointer IFNE H6309 pulsw
--- a/rules.mak Mon Dec 10 16:27:38 2012 -0600 +++ b/rules.mak Tue Jan 22 19:14:52 2013 -0600 @@ -69,13 +69,13 @@ IDENT_SHORT = $(IDENT) -s #UNIX2OS9 = u2o #OS92UNIX = o2u -OS9FORMAT = os9 format -OS9FORMAT_SS35 = os9 format -t35 -ss -dd -OS9FORMAT_SS40 = os9 format -t40 -ss -dd -OS9FORMAT_SS80 = os9 format -t80 -ss -dd -OS9FORMAT_DS40 = os9 format -t40 -ds -dd -OS9FORMAT_DS80 = os9 format -t80 -ds -dd -OS9FORMAT_DW = os9 format -t1024 -ss -dd +OS9FORMAT = os9 format -e +OS9FORMAT_SS35 = os9 format -e -t35 -ss -dd +OS9FORMAT_SS40 = os9 format -e -t40 -ss -dd +OS9FORMAT_SS80 = os9 format -e -t80 -ss -dd +OS9FORMAT_DS40 = os9 format -e -t40 -ds -dd +OS9FORMAT_DS80 = os9 format -e -t80 -ds -dd +OS9FORMAT_DW = os9 format -e -t1024 -ss -dd OS9GEN = os9 gen OS9RENAME = os9 rename OS9ATTR = os9 attr -q