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0
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1 /* 6809 Simulator V09.
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2
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3 created 1994,1995 by L.C. Benschop.
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4 copyleft (c) 1994-2014 by the sbc09 team, see AUTHORS for more details.
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5 license: GNU General Public License version 2, see LICENSE for more details.
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6
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7 This program simulates a 6809 processor.
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8
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9 System dependencies: short must be 16 bits.
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10 char must be 8 bits.
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11 long must be more than 16 bits.
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12 arrays up to 65536 bytes must be supported.
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13 machine must be twos complement.
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14 Most Unix machines will work. For MSODS you need long pointers
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15 and you may have to malloc() the mem array of 65536 bytes.
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16
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17 Special instructions:
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18 SWI2 writes char to stdout from register B.
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19 SWI3 reads char from stdout to register B, sets carry at EOF.
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20 (or when no key available when using term control).
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21 SWI retains its normal function.
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22 CWAI and SYNC stop simulator.
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23 Note: special instructions are gone for now.
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24
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25 ACIA emulation at port $E000
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26
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27 Note: BIG_ENDIAN option is no longer needed.
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28 */
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29
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30 #include <stdio.h>
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31 #include <unistd.h>
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32
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33 #define engine
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34 #include "v09.h"
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35
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36 #define USLEEP 1000
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37 Byte aca,acb;
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38 Byte *breg=&aca,*areg=&acb;
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39 static int tracetrick=0;
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9
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40 extern long romstart;
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0
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41
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21
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42 #ifndef USE_MMU
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43
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44 static Byte mem1(Word adr) {
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45 if ((adr&0xfe00)==(IOPAGE&0xfe00)) return do_input(adr&0x1ff);
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46 return mem[adr];
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47 }
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48
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49 static void SETBYTE1(Word a,Byte n) {
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50 if ((a&0xfe00)==(IOPAGE&0xfe00)) do_output(a&0x1ff,n);
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51 if(!(a>=romstart))mem[a]=n;
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52 }
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53 #define mem(a) mem1(a)
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54 #define SETBYTE(a,n) SETBYTE1(a,n);
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55
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56 #else
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57
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58 int paddr(Word adr, Byte *immu) {
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85
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59 if ((adr&0xfe00)==(IOPAGE&0xfe00)) return 0x38*0x2000+adr;
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21
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60 return (immu[ (adr) >> 13 ] <<13 ) + ((adr) & 0x1fff );
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61 }
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10
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62
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11
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63 Byte * mem0(Byte *iphymem, Word adr, Byte *immu) {
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21
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64 return & iphymem[ paddr(adr,immu) ];
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18
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65 }
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11
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66
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23
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67 Byte mem1(Byte *iphymem, Word adr, Byte *immu) {
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18
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68 if ((adr&0xfe00)==(IOPAGE&0xfe00)) return do_input(adr&0x1ff);
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11
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69 Byte *p = mem0(iphymem, adr, immu);
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16
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70 if(!(p-phymem>=rommemsize)) {
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11
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71 return *p;
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72 } else {
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73 return 0xff;
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74 }
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75 }
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9
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76
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11
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77 #define mem(a) mem1(iphymem,a,immu)
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78
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23
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79 Byte * SETBYTE1(Word a,Byte n, Byte *iphymem, Byte *immu) {
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80 Word adr = a;
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81 if ((adr&0xfe00)==(IOPAGE&0xfe00)) {
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82 do_output(adr&0x1ff,n);
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83 return mmu;
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84 } else {
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85 Byte *p = mem0(iphymem, adr,immu);
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86 if(!(p-phymem>=romstart)) {
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87 *p=n;
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88 }
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89 }
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90 return immu;
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18
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91 }
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11
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92
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23
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93 #define SETBYTE(a,n) immu=SETBYTE1(a,n,iphymem,immu);
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94
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11
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95 #endif
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4
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96
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97 #define GETWORD(a) (mem(a)<<8|mem((a)+1))
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11
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98 #define SETWORD(a,n) {Word a1=a;SETBYTE(a1,n>>8);SETBYTE(a1+1,n);}
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9
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99
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11
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100 /* Macros for load and store of accumulators. Can be modified to check
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101 for port addresses */
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102 // #define LOADAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))reg=mem(eaddr);else\
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103 // reg=do_input(eaddr&0xff);
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104 // #define STOREAC(reg) if((eaddr&0xff00)!=(IOPAGE&0xff00))SETBYTE(eaddr,reg)else\
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105 // do_output(eaddr&0xff,reg);
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9
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106
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0
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107 /* Two bytes of a word are fetched separately because of
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108 the possible wrap-around at address $ffff and alignment
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109 */
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110
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4
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111 #define IMMBYTE(b) b=mem(ipcreg++);
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0
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112 #define IMMWORD(w) {w=GETWORD(ipcreg);ipcreg+=2;}
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113
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114 #define PUSHBYTE(b) {--isreg;SETBYTE(isreg,b)}
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115 #define PUSHWORD(w) {isreg-=2;SETWORD(isreg,w)}
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4
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116 #define PULLBYTE(b) b=mem(isreg++);
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0
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117 #define PULLWORD(w) {w=GETWORD(isreg);isreg+=2;}
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118 #define PSHUBYTE(b) {--iureg;SETBYTE(iureg,b)}
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119 #define PSHUWORD(w) {iureg-=2;SETWORD(iureg,w)}
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4
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120 #define PULUBYTE(b) b=mem(iureg++);
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0
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121 #define PULUWORD(w) {w=GETWORD(iureg);iureg+=2;}
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122
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123 #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b))
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124
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125 #define GETDREG ((iareg<<8)|ibreg)
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126 #define SETDREG(n) {iareg=(n)>>8;ibreg=(n);}
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127
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128 /* Macros for addressing modes (postbytes have their own code) */
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129 #define DIRECT {IMMBYTE(eaddr) eaddr|=(idpreg<<8);}
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130 #define IMM8 {eaddr=ipcreg++;}
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131 #define IMM16 {eaddr=ipcreg;ipcreg+=2;}
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132 #define EXTENDED {IMMWORD(eaddr)}
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133
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134 /* macros to set status flags */
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135 #define SEC iccreg|=0x01;
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136 #define CLC iccreg&=0xfe;
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137 #define SEZ iccreg|=0x04;
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138 #define CLZ iccreg&=0xfb;
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139 #define SEN iccreg|=0x08;
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140 #define CLN iccreg&=0xf7;
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141 #define SEV iccreg|=0x02;
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142 #define CLV iccreg&=0xfd;
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143 #define SEH iccreg|=0x20;
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144 #define CLH iccreg&=0xdf;
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145
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146 /* set N and Z flags depending on 8 or 16 bit result */
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147 #define SETNZ8(b) {if(b)CLZ else SEZ if(b&0x80)SEN else CLN}
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148 #define SETNZ16(b) {if(b)CLZ else SEZ if(b&0x8000)SEN else CLN}
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149
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150 #define SETSTATUS(a,b,res) if((a^b^res)&0x10) SEH else CLH \
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151 if((a^b^res^(res>>1))&0x80)SEV else CLV \
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152 if(res&0x100)SEC else CLC SETNZ8((Byte)res)
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153
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154 #define SETSTATUSD(a,b,res) {if(res&0x10000) SEC else CLC \
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155 if(((res>>1)^a^b^res)&0x8000) SEV else CLV \
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156 SETNZ16((Word)res)}
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157
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158 /* Macros for branch instructions */
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159 #define BRANCH(f) if(!iflag){IMMBYTE(tb) if(f)ipcreg+=SIGNED(tb);}\
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160 else{IMMWORD(tw) if(f)ipcreg+=tw;}
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161 #define NXORV ((iccreg&0x08)^((iccreg&0x02)<<2))
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162
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163 /* MAcros for setting/getting registers in TFR/EXG instructions */
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164 #define GETREG(val,reg) switch(reg) {\
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165 case 0: val=GETDREG;break;\
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166 case 1: val=ixreg;break;\
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167 case 2: val=iyreg;break;\
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168 case 3: val=iureg;break;\
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169 case 4: val=isreg;break;\
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170 case 5: val=ipcreg;break;\
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171 case 8: val=iareg;break;\
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172 case 9: val=ibreg;break;\
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173 case 10: val=iccreg;break;\
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174 case 11: val=idpreg;break;}
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175
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176 #define SETREG(val,reg) switch(reg) {\
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177 case 0: SETDREG(val) break;\
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178 case 1: ixreg=val;break;\
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179 case 2: iyreg=val;break;\
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180 case 3: iureg=val;break;\
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181 case 4: isreg=val;break;\
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182 case 5: ipcreg=val;break;\
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183 case 8: iareg=val;break;\
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184 case 9: ibreg=val;break;\
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185 case 10: iccreg=val;break;\
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186 case 11: idpreg=val;break;}
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187
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11
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188
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189 #define LOADAC(reg) reg=mem(eaddr);
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190 #define STOREAC(reg) SETBYTE(eaddr,reg);
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0
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191
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192 #define LOADREGS ixreg=xreg;iyreg=yreg;\
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193 iureg=ureg;isreg=sreg;\
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194 ipcreg=pcreg;\
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195 iareg=*areg;ibreg=*breg;\
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4
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196 idpreg=dpreg;iccreg=ccreg;immu=mmu;
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0
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197
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198 #define SAVEREGS xreg=ixreg;yreg=iyreg;\
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199 ureg=iureg;sreg=isreg;\
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200 pcreg=ipcreg;\
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201 *areg=iareg;*breg=ibreg;\
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4
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202 dpreg=idpreg;ccreg=iccreg;mmu=immu;
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0
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203
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204
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205 unsigned char haspostbyte[] = {
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206 /*0*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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207 /*1*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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208 /*2*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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209 /*3*/ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,
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210 /*4*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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211 /*5*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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212 /*6*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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213 /*7*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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214 /*8*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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215 /*9*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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216 /*A*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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217 /*B*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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218 /*C*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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219 /*D*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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220 /*E*/ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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221 /*F*/ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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222 };
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223
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9
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224 extern char *prog ;
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225
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0
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226 void interpr(void)
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227 {
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228 Word ixreg,iyreg,iureg,isreg,ipcreg;
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229 Byte idpreg,iccreg,iareg,ibreg;
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230 /* Make local variables for the registers. On a real processor (non-Intel)
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231 these could be implemented as fast registers. */
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232 Word eaddr; /* effective address */
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233 Byte ireg; /* instruction register */
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234 Byte iflag; /* flag to indicate $10 or $11 prebyte */
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235 Byte tb;Word tw;
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4
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236 Byte *immu = 0;
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237 #ifdef USE_MMU
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238 Byte *iphymem = (Byte *)phymem;
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239 #endif
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0
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240 LOADREGS
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241 for(;;){
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242 if(attention) {
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9
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243 if(tracing && ipcreg>=tracelo && ipcreg<=tracehi) {
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244 SAVEREGS
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245 #ifdef USE_MMU
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18
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246 Byte *phyadr = mem0(phymem,ipcreg,immu);
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247 prog = (char *)(phyadr - ipcreg);
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9
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248 #endif
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249 do_trace(tracefile);
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250 }
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0
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251 if(irq) {
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252 if(irq==1&&!(iccreg&0x10)) { /* standard IRQ */
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253 PUSHWORD(ipcreg)
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254 PUSHWORD(iureg)
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255 PUSHWORD(iyreg)
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256 PUSHWORD(ixreg)
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257 PUSHBYTE(idpreg)
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258 PUSHBYTE(ibreg)
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259 PUSHBYTE(iareg)
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13
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260 iccreg|=0x80;
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0
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261 PUSHBYTE(iccreg)
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262 iccreg|=0x90;
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263 ipcreg=GETWORD(0xfff8);
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264 }
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265 if(irq==2&&!(iccreg&0x40)) { /* Fast IRQ */
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266 PUSHWORD(ipcreg)
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13
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267 iccreg&=0x7f;
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0
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268 PUSHBYTE(iccreg)
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269 iccreg|=0x50;
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270 ipcreg=GETWORD(0xfff6);
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271 }
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272 if(!tracing)attention=0;
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273 irq=0;
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274 }
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275 }
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53
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276 if(escape){ SAVEREGS do_escape(); LOADREGS }
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0
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277 iflag=0;
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278 flaginstr: /* $10 and $11 instructions return here */
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4
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279 ireg=mem(ipcreg++);
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0
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280 if(haspostbyte[ireg]) {
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4
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281 Byte postbyte=mem(ipcreg++);
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0
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282 switch(postbyte) {
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283 case 0x00: eaddr=ixreg;break;
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284 case 0x01: eaddr=ixreg+1;break;
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285 case 0x02: eaddr=ixreg+2;break;
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286 case 0x03: eaddr=ixreg+3;break;
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287 case 0x04: eaddr=ixreg+4;break;
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288 case 0x05: eaddr=ixreg+5;break;
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289 case 0x06: eaddr=ixreg+6;break;
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290 case 0x07: eaddr=ixreg+7;break;
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291 case 0x08: eaddr=ixreg+8;break;
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292 case 0x09: eaddr=ixreg+9;break;
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293 case 0x0A: eaddr=ixreg+10;break;
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294 case 0x0B: eaddr=ixreg+11;break;
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295 case 0x0C: eaddr=ixreg+12;break;
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296 case 0x0D: eaddr=ixreg+13;break;
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297 case 0x0E: eaddr=ixreg+14;break;
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298 case 0x0F: eaddr=ixreg+15;break;
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299 case 0x10: eaddr=ixreg-16;break;
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300 case 0x11: eaddr=ixreg-15;break;
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301 case 0x12: eaddr=ixreg-14;break;
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302 case 0x13: eaddr=ixreg-13;break;
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303 case 0x14: eaddr=ixreg-12;break;
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304 case 0x15: eaddr=ixreg-11;break;
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305 case 0x16: eaddr=ixreg-10;break;
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306 case 0x17: eaddr=ixreg-9;break;
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307 case 0x18: eaddr=ixreg-8;break;
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308 case 0x19: eaddr=ixreg-7;break;
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309 case 0x1A: eaddr=ixreg-6;break;
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310 case 0x1B: eaddr=ixreg-5;break;
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311 case 0x1C: eaddr=ixreg-4;break;
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312 case 0x1D: eaddr=ixreg-3;break;
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313 case 0x1E: eaddr=ixreg-2;break;
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314 case 0x1F: eaddr=ixreg-1;break;
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315 case 0x20: eaddr=iyreg;break;
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316 case 0x21: eaddr=iyreg+1;break;
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317 case 0x22: eaddr=iyreg+2;break;
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318 case 0x23: eaddr=iyreg+3;break;
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319 case 0x24: eaddr=iyreg+4;break;
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320 case 0x25: eaddr=iyreg+5;break;
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321 case 0x26: eaddr=iyreg+6;break;
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322 case 0x27: eaddr=iyreg+7;break;
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323 case 0x28: eaddr=iyreg+8;break;
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324 case 0x29: eaddr=iyreg+9;break;
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325 case 0x2A: eaddr=iyreg+10;break;
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326 case 0x2B: eaddr=iyreg+11;break;
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327 case 0x2C: eaddr=iyreg+12;break;
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328 case 0x2D: eaddr=iyreg+13;break;
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329 case 0x2E: eaddr=iyreg+14;break;
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330 case 0x2F: eaddr=iyreg+15;break;
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331 case 0x30: eaddr=iyreg-16;break;
|
|
|
332 case 0x31: eaddr=iyreg-15;break;
|
|
|
333 case 0x32: eaddr=iyreg-14;break;
|
|
|
334 case 0x33: eaddr=iyreg-13;break;
|
|
|
335 case 0x34: eaddr=iyreg-12;break;
|
|
|
336 case 0x35: eaddr=iyreg-11;break;
|
|
|
337 case 0x36: eaddr=iyreg-10;break;
|
|
|
338 case 0x37: eaddr=iyreg-9;break;
|
|
|
339 case 0x38: eaddr=iyreg-8;break;
|
|
|
340 case 0x39: eaddr=iyreg-7;break;
|
|
|
341 case 0x3A: eaddr=iyreg-6;break;
|
|
|
342 case 0x3B: eaddr=iyreg-5;break;
|
|
|
343 case 0x3C: eaddr=iyreg-4;break;
|
|
|
344 case 0x3D: eaddr=iyreg-3;break;
|
|
|
345 case 0x3E: eaddr=iyreg-2;break;
|
|
|
346 case 0x3F: eaddr=iyreg-1;break;
|
|
|
347 case 0x40: eaddr=iureg;break;
|
|
|
348 case 0x41: eaddr=iureg+1;break;
|
|
|
349 case 0x42: eaddr=iureg+2;break;
|
|
|
350 case 0x43: eaddr=iureg+3;break;
|
|
|
351 case 0x44: eaddr=iureg+4;break;
|
|
|
352 case 0x45: eaddr=iureg+5;break;
|
|
|
353 case 0x46: eaddr=iureg+6;break;
|
|
|
354 case 0x47: eaddr=iureg+7;break;
|
|
|
355 case 0x48: eaddr=iureg+8;break;
|
|
|
356 case 0x49: eaddr=iureg+9;break;
|
|
|
357 case 0x4A: eaddr=iureg+10;break;
|
|
|
358 case 0x4B: eaddr=iureg+11;break;
|
|
|
359 case 0x4C: eaddr=iureg+12;break;
|
|
|
360 case 0x4D: eaddr=iureg+13;break;
|
|
|
361 case 0x4E: eaddr=iureg+14;break;
|
|
|
362 case 0x4F: eaddr=iureg+15;break;
|
|
|
363 case 0x50: eaddr=iureg-16;break;
|
|
|
364 case 0x51: eaddr=iureg-15;break;
|
|
|
365 case 0x52: eaddr=iureg-14;break;
|
|
|
366 case 0x53: eaddr=iureg-13;break;
|
|
|
367 case 0x54: eaddr=iureg-12;break;
|
|
|
368 case 0x55: eaddr=iureg-11;break;
|
|
|
369 case 0x56: eaddr=iureg-10;break;
|
|
|
370 case 0x57: eaddr=iureg-9;break;
|
|
|
371 case 0x58: eaddr=iureg-8;break;
|
|
|
372 case 0x59: eaddr=iureg-7;break;
|
|
|
373 case 0x5A: eaddr=iureg-6;break;
|
|
|
374 case 0x5B: eaddr=iureg-5;break;
|
|
|
375 case 0x5C: eaddr=iureg-4;break;
|
|
|
376 case 0x5D: eaddr=iureg-3;break;
|
|
|
377 case 0x5E: eaddr=iureg-2;break;
|
|
|
378 case 0x5F: eaddr=iureg-1;break;
|
|
|
379 case 0x60: eaddr=isreg;break;
|
|
|
380 case 0x61: eaddr=isreg+1;break;
|
|
|
381 case 0x62: eaddr=isreg+2;break;
|
|
|
382 case 0x63: eaddr=isreg+3;break;
|
|
|
383 case 0x64: eaddr=isreg+4;break;
|
|
|
384 case 0x65: eaddr=isreg+5;break;
|
|
|
385 case 0x66: eaddr=isreg+6;break;
|
|
|
386 case 0x67: eaddr=isreg+7;break;
|
|
|
387 case 0x68: eaddr=isreg+8;break;
|
|
|
388 case 0x69: eaddr=isreg+9;break;
|
|
|
389 case 0x6A: eaddr=isreg+10;break;
|
|
|
390 case 0x6B: eaddr=isreg+11;break;
|
|
|
391 case 0x6C: eaddr=isreg+12;break;
|
|
|
392 case 0x6D: eaddr=isreg+13;break;
|
|
|
393 case 0x6E: eaddr=isreg+14;break;
|
|
|
394 case 0x6F: eaddr=isreg+15;break;
|
|
|
395 case 0x70: eaddr=isreg-16;break;
|
|
|
396 case 0x71: eaddr=isreg-15;break;
|
|
|
397 case 0x72: eaddr=isreg-14;break;
|
|
|
398 case 0x73: eaddr=isreg-13;break;
|
|
|
399 case 0x74: eaddr=isreg-12;break;
|
|
|
400 case 0x75: eaddr=isreg-11;break;
|
|
|
401 case 0x76: eaddr=isreg-10;break;
|
|
|
402 case 0x77: eaddr=isreg-9;break;
|
|
|
403 case 0x78: eaddr=isreg-8;break;
|
|
|
404 case 0x79: eaddr=isreg-7;break;
|
|
|
405 case 0x7A: eaddr=isreg-6;break;
|
|
|
406 case 0x7B: eaddr=isreg-5;break;
|
|
|
407 case 0x7C: eaddr=isreg-4;break;
|
|
|
408 case 0x7D: eaddr=isreg-3;break;
|
|
|
409 case 0x7E: eaddr=isreg-2;break;
|
|
|
410 case 0x7F: eaddr=isreg-1;break;
|
|
|
411 case 0x80: eaddr=ixreg;ixreg++;break;
|
|
|
412 case 0x81: eaddr=ixreg;ixreg+=2;break;
|
|
|
413 case 0x82: ixreg--;eaddr=ixreg;break;
|
|
|
414 case 0x83: ixreg-=2;eaddr=ixreg;break;
|
|
|
415 case 0x84: eaddr=ixreg;break;
|
|
|
416 case 0x85: eaddr=ixreg+SIGNED(ibreg);break;
|
|
|
417 case 0x86: eaddr=ixreg+SIGNED(iareg);break;
|
|
|
418 case 0x87: eaddr=0;break; /*ILELGAL*/
|
|
|
419 case 0x88: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);break;
|
|
|
420 case 0x89: IMMWORD(eaddr);eaddr+=ixreg;break;
|
|
|
421 case 0x8A: eaddr=0;break; /*ILLEGAL*/
|
|
|
422 case 0x8B: eaddr=ixreg+GETDREG;break;
|
|
|
423 case 0x8C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
424 case 0x8D: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
425 case 0x8E: eaddr=0;break; /*ILLEGAL*/
|
|
|
426 case 0x8F: IMMWORD(eaddr);break;
|
|
|
427 case 0x90: eaddr=ixreg;ixreg++;eaddr=GETWORD(eaddr);break;
|
|
|
428 case 0x91: eaddr=ixreg;ixreg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
429 case 0x92: ixreg--;eaddr=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
430 case 0x93: ixreg-=2;eaddr=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
431 case 0x94: eaddr=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
432 case 0x95: eaddr=ixreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
433 case 0x96: eaddr=ixreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
434 case 0x97: eaddr=0;break; /*ILELGAL*/
|
|
|
435 case 0x98: IMMBYTE(eaddr);eaddr=ixreg+SIGNED(eaddr);
|
|
|
436 eaddr=GETWORD(eaddr);break;
|
|
|
437 case 0x99: IMMWORD(eaddr);eaddr+=ixreg;eaddr=GETWORD(eaddr);break;
|
|
|
438 case 0x9A: eaddr=0;break; /*ILLEGAL*/
|
|
|
439 case 0x9B: eaddr=ixreg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
440 case 0x9C: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
441 eaddr=GETWORD(eaddr);break;
|
|
|
442 case 0x9D: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
443 case 0x9E: eaddr=0;break; /*ILLEGAL*/
|
|
|
444 case 0x9F: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
445 case 0xA0: eaddr=iyreg;iyreg++;break;
|
|
|
446 case 0xA1: eaddr=iyreg;iyreg+=2;break;
|
|
|
447 case 0xA2: iyreg--;eaddr=iyreg;break;
|
|
|
448 case 0xA3: iyreg-=2;eaddr=iyreg;break;
|
|
|
449 case 0xA4: eaddr=iyreg;break;
|
|
|
450 case 0xA5: eaddr=iyreg+SIGNED(ibreg);break;
|
|
|
451 case 0xA6: eaddr=iyreg+SIGNED(iareg);break;
|
|
|
452 case 0xA7: eaddr=0;break; /*ILELGAL*/
|
|
|
453 case 0xA8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);break;
|
|
|
454 case 0xA9: IMMWORD(eaddr);eaddr+=iyreg;break;
|
|
|
455 case 0xAA: eaddr=0;break; /*ILLEGAL*/
|
|
|
456 case 0xAB: eaddr=iyreg+GETDREG;break;
|
|
|
457 case 0xAC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
458 case 0xAD: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
459 case 0xAE: eaddr=0;break; /*ILLEGAL*/
|
|
|
460 case 0xAF: IMMWORD(eaddr);break;
|
|
|
461 case 0xB0: eaddr=iyreg;iyreg++;eaddr=GETWORD(eaddr);break;
|
|
|
462 case 0xB1: eaddr=iyreg;iyreg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
463 case 0xB2: iyreg--;eaddr=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
464 case 0xB3: iyreg-=2;eaddr=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
465 case 0xB4: eaddr=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
466 case 0xB5: eaddr=iyreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
467 case 0xB6: eaddr=iyreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
468 case 0xB7: eaddr=0;break; /*ILELGAL*/
|
|
|
469 case 0xB8: IMMBYTE(eaddr);eaddr=iyreg+SIGNED(eaddr);
|
|
|
470 eaddr=GETWORD(eaddr);break;
|
|
|
471 case 0xB9: IMMWORD(eaddr);eaddr+=iyreg;eaddr=GETWORD(eaddr);break;
|
|
|
472 case 0xBA: eaddr=0;break; /*ILLEGAL*/
|
|
|
473 case 0xBB: eaddr=iyreg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
474 case 0xBC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
475 eaddr=GETWORD(eaddr);break;
|
|
|
476 case 0xBD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
477 case 0xBE: eaddr=0;break; /*ILLEGAL*/
|
|
|
478 case 0xBF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
479 case 0xC0: eaddr=iureg;iureg++;break;
|
|
|
480 case 0xC1: eaddr=iureg;iureg+=2;break;
|
|
|
481 case 0xC2: iureg--;eaddr=iureg;break;
|
|
|
482 case 0xC3: iureg-=2;eaddr=iureg;break;
|
|
|
483 case 0xC4: eaddr=iureg;break;
|
|
|
484 case 0xC5: eaddr=iureg+SIGNED(ibreg);break;
|
|
|
485 case 0xC6: eaddr=iureg+SIGNED(iareg);break;
|
|
|
486 case 0xC7: eaddr=0;break; /*ILELGAL*/
|
|
|
487 case 0xC8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);break;
|
|
|
488 case 0xC9: IMMWORD(eaddr);eaddr+=iureg;break;
|
|
|
489 case 0xCA: eaddr=0;break; /*ILLEGAL*/
|
|
|
490 case 0xCB: eaddr=iureg+GETDREG;break;
|
|
|
491 case 0xCC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
492 case 0xCD: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
493 case 0xCE: eaddr=0;break; /*ILLEGAL*/
|
|
|
494 case 0xCF: IMMWORD(eaddr);break;
|
|
|
495 case 0xD0: eaddr=iureg;iureg++;eaddr=GETWORD(eaddr);break;
|
|
|
496 case 0xD1: eaddr=iureg;iureg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
497 case 0xD2: iureg--;eaddr=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
498 case 0xD3: iureg-=2;eaddr=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
499 case 0xD4: eaddr=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
500 case 0xD5: eaddr=iureg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
501 case 0xD6: eaddr=iureg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
502 case 0xD7: eaddr=0;break; /*ILELGAL*/
|
|
|
503 case 0xD8: IMMBYTE(eaddr);eaddr=iureg+SIGNED(eaddr);
|
|
|
504 eaddr=GETWORD(eaddr);break;
|
|
|
505 case 0xD9: IMMWORD(eaddr);eaddr+=iureg;eaddr=GETWORD(eaddr);break;
|
|
|
506 case 0xDA: eaddr=0;break; /*ILLEGAL*/
|
|
|
507 case 0xDB: eaddr=iureg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
508 case 0xDC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
509 eaddr=GETWORD(eaddr);break;
|
|
|
510 case 0xDD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
511 case 0xDE: eaddr=0;break; /*ILLEGAL*/
|
|
|
512 case 0xDF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
513 case 0xE0: eaddr=isreg;isreg++;break;
|
|
|
514 case 0xE1: eaddr=isreg;isreg+=2;break;
|
|
|
515 case 0xE2: isreg--;eaddr=isreg;break;
|
|
|
516 case 0xE3: isreg-=2;eaddr=isreg;break;
|
|
|
517 case 0xE4: eaddr=isreg;break;
|
|
|
518 case 0xE5: eaddr=isreg+SIGNED(ibreg);break;
|
|
|
519 case 0xE6: eaddr=isreg+SIGNED(iareg);break;
|
|
|
520 case 0xE7: eaddr=0;break; /*ILELGAL*/
|
|
|
521 case 0xE8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);break;
|
|
|
522 case 0xE9: IMMWORD(eaddr);eaddr+=isreg;break;
|
|
|
523 case 0xEA: eaddr=0;break; /*ILLEGAL*/
|
|
|
524 case 0xEB: eaddr=isreg+GETDREG;break;
|
|
|
525 case 0xEC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);break;
|
|
|
526 case 0xED: IMMWORD(eaddr);eaddr+=ipcreg;break;
|
|
|
527 case 0xEE: eaddr=0;break; /*ILLEGAL*/
|
|
|
528 case 0xEF: IMMWORD(eaddr);break;
|
|
|
529 case 0xF0: eaddr=isreg;isreg++;eaddr=GETWORD(eaddr);break;
|
|
|
530 case 0xF1: eaddr=isreg;isreg+=2;eaddr=GETWORD(eaddr);break;
|
|
|
531 case 0xF2: isreg--;eaddr=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
532 case 0xF3: isreg-=2;eaddr=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
533 case 0xF4: eaddr=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
534 case 0xF5: eaddr=isreg+SIGNED(ibreg);eaddr=GETWORD(eaddr);break;
|
|
|
535 case 0xF6: eaddr=isreg+SIGNED(iareg);eaddr=GETWORD(eaddr);break;
|
|
|
536 case 0xF7: eaddr=0;break; /*ILELGAL*/
|
|
|
537 case 0xF8: IMMBYTE(eaddr);eaddr=isreg+SIGNED(eaddr);
|
|
|
538 eaddr=GETWORD(eaddr);break;
|
|
|
539 case 0xF9: IMMWORD(eaddr);eaddr+=isreg;eaddr=GETWORD(eaddr);break;
|
|
|
540 case 0xFA: eaddr=0;break; /*ILLEGAL*/
|
|
|
541 case 0xFB: eaddr=isreg+GETDREG;eaddr=GETWORD(eaddr);break;
|
|
|
542 case 0xFC: IMMBYTE(eaddr);eaddr=ipcreg+SIGNED(eaddr);
|
|
|
543 eaddr=GETWORD(eaddr);break;
|
|
|
544 case 0xFD: IMMWORD(eaddr);eaddr+=ipcreg;eaddr=GETWORD(eaddr);break;
|
|
|
545 case 0xFE: eaddr=0;break; /*ILLEGAL*/
|
|
|
546 case 0xFF: IMMWORD(eaddr);eaddr=GETWORD(eaddr);break;
|
|
|
547 }
|
|
|
548 }
|
|
|
549 switch(ireg) {
|
|
4
|
550 case 0x00: /*NEG direct*/ DIRECT tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw)
|
|
0
|
551 SETBYTE(eaddr,tw)break;
|
|
|
552 case 0x01: break;/*ILLEGAL*/
|
|
|
553 case 0x02: break;/*ILLEGAL*/
|
|
4
|
554 case 0x03: /*COM direct*/ DIRECT tb=~mem(eaddr);SETNZ8(tb);SEC CLV
|
|
0
|
555 SETBYTE(eaddr,tb)break;
|
|
4
|
556 case 0x04: /*LSR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC
|
|
0
|
557 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
558 SETBYTE(eaddr,tb)break;
|
|
|
559 case 0x05: break;/* ILLEGAL*/
|
|
|
560 case 0x06: /*ROR direct*/ DIRECT tb=(iccreg&0x01)<<7;
|
|
4
|
561 if(mem(eaddr)&0x01)SEC else CLC
|
|
|
562 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw)
|
|
0
|
563 SETBYTE(eaddr,tw)
|
|
|
564 break;
|
|
4
|
565 case 0x07: /*ASR direct*/ DIRECT tb=mem(eaddr);if(tb&0x01)SEC else CLC
|
|
0
|
566 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
567 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
|
|
|
568 break;
|
|
4
|
569 case 0x08: /*ASL direct*/ DIRECT tw=mem(eaddr)<<1;
|
|
|
570 SETSTATUS(mem(eaddr),mem(eaddr),tw)
|
|
0
|
571 SETBYTE(eaddr,tw)break;
|
|
4
|
572 case 0x09: /*ROL direct*/ DIRECT tb=mem(eaddr);tw=iccreg&0x01;
|
|
0
|
573 if(tb&0x80)SEC else CLC
|
|
|
574 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
575 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
4
|
576 case 0x0A: /*DEC direct*/ DIRECT tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV
|
|
0
|
577 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
578 case 0x0B: break; /*ILLEGAL*/
|
|
4
|
579 case 0x0C: /*INC direct*/ DIRECT tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV
|
|
0
|
580 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
4
|
581 case 0x0D: /*TST direct*/ DIRECT tb=mem(eaddr);SETNZ8(tb) break;
|
|
0
|
582 case 0x0E: /*JMP direct*/ DIRECT ipcreg=eaddr;break;
|
|
|
583 case 0x0F: /*CLR direct*/ DIRECT SETBYTE(eaddr,0);CLN CLV SEZ CLC break;
|
|
|
584 case 0x10: /* flag10 */ iflag=1;goto flaginstr;
|
|
|
585 case 0x11: /* flag11 */ iflag=2;goto flaginstr;
|
|
|
586 case 0x12: /* NOP */ break;
|
|
|
587 case 0x13: /* SYNC */
|
|
|
588 do usleep(USLEEP); /* Wait for IRQ */
|
|
|
589 while(!irq && !attention);
|
|
|
590 if(iccreg&0x40)tracetrick=1;
|
|
|
591 break;
|
|
|
592 case 0x14: break; /*ILLEGAL*/
|
|
|
593 case 0x15: break; /*ILLEGAL*/
|
|
|
594 case 0x16: /*LBRA*/ IMMWORD(eaddr) ipcreg+=eaddr;break;
|
|
|
595 case 0x17: /*LBSR*/ IMMWORD(eaddr) PUSHWORD(ipcreg) ipcreg+=eaddr;break;
|
|
|
596 case 0x18: break; /*ILLEGAL*/
|
|
|
597 case 0x19: /* DAA*/ tw=iareg;
|
|
|
598 if(iccreg&0x20)tw+=6;
|
|
|
599 if((tw&0x0f)>9)tw+=6;
|
|
|
600 if(iccreg&0x01)tw+=0x60;
|
|
|
601 if((tw&0xf0)>0x90)tw+=0x60;
|
|
|
602 if(tw&0x100)SEC
|
|
|
603 iareg=tw;break;
|
|
|
604 case 0x1A: /* ORCC*/ IMMBYTE(tb) iccreg|=tb;break;
|
|
|
605 case 0x1B: break; /*ILLEGAL*/
|
|
|
606 case 0x1C: /* ANDCC*/ IMMBYTE(tb) iccreg&=tb;break;
|
|
|
607 case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break;
|
|
|
608 case 0x1E: /* EXG */ IMMBYTE(tb) {Word t2;GETREG(tw,tb>>4) GETREG(t2,tb&15)
|
|
|
609 SETREG(t2,tb>>4) SETREG(tw,tb&15) } break;
|
|
|
610 case 0x1F: /* TFR */ IMMBYTE(tb) GETREG(tw,tb>>4) SETREG(tw,tb&15) break;
|
|
|
611 case 0x20: /* (L)BRA*/ BRANCH(1) break;
|
|
|
612 case 0x21: /* (L)BRN*/ BRANCH(0) break;
|
|
|
613 case 0x22: /* (L)BHI*/ BRANCH(!(iccreg&0x05)) break;
|
|
|
614 case 0x23: /* (L)BLS*/ BRANCH(iccreg&0x05) break;
|
|
|
615 case 0x24: /* (L)BCC*/ BRANCH(!(iccreg&0x01)) break;
|
|
|
616 case 0x25: /* (L)BCS*/ BRANCH(iccreg&0x01) break;
|
|
|
617 case 0x26: /* (L)BNE*/ BRANCH(!(iccreg&0x04)) break;
|
|
|
618 case 0x27: /* (L)BEQ*/ BRANCH(iccreg&0x04) break;
|
|
|
619 case 0x28: /* (L)BVC*/ BRANCH(!(iccreg&0x02)) break;
|
|
|
620 case 0x29: /* (L)BVS*/ BRANCH(iccreg&0x02) break;
|
|
|
621 case 0x2A: /* (L)BPL*/ BRANCH(!(iccreg&0x08)) break;
|
|
|
622 case 0x2B: /* (L)BMI*/ BRANCH(iccreg&0x08) break;
|
|
|
623 case 0x2C: /* (L)BGE*/ BRANCH(!NXORV) break;
|
|
|
624 case 0x2D: /* (L)BLT*/ BRANCH(NXORV) break;
|
|
|
625 case 0x2E: /* (L)BGT*/ BRANCH(!(NXORV||iccreg&0x04)) break;
|
|
|
626 case 0x2F: /* (L)BLE*/ BRANCH(NXORV||iccreg&0x04) break;
|
|
|
627 case 0x30: /* LEAX*/ ixreg=eaddr; if(ixreg) CLZ else SEZ break;
|
|
|
628 case 0x31: /* LEAY*/ iyreg=eaddr; if(iyreg) CLZ else SEZ break;
|
|
|
629 case 0x32: /* LEAS*/ isreg=eaddr;break;
|
|
|
630 case 0x33: /* LEAU*/ iureg=eaddr;break;
|
|
|
631 case 0x34: /* PSHS*/ IMMBYTE(tb)
|
|
|
632 if(tb&0x80)PUSHWORD(ipcreg)
|
|
|
633 if(tb&0x40)PUSHWORD(iureg)
|
|
|
634 if(tb&0x20)PUSHWORD(iyreg)
|
|
|
635 if(tb&0x10)PUSHWORD(ixreg)
|
|
|
636 if(tb&0x08)PUSHBYTE(idpreg)
|
|
|
637 if(tb&0x04)PUSHBYTE(ibreg)
|
|
|
638 if(tb&0x02)PUSHBYTE(iareg)
|
|
|
639 if(tb&0x01)PUSHBYTE(iccreg) break;
|
|
|
640 case 0x35: /* PULS*/ IMMBYTE(tb)
|
|
|
641 if(tb&0x01)PULLBYTE(iccreg)
|
|
|
642 if(tb&0x02)PULLBYTE(iareg)
|
|
|
643 if(tb&0x04)PULLBYTE(ibreg)
|
|
|
644 if(tb&0x08)PULLBYTE(idpreg)
|
|
|
645 if(tb&0x10)PULLWORD(ixreg)
|
|
|
646 if(tb&0x20)PULLWORD(iyreg)
|
|
|
647 if(tb&0x40)PULLWORD(iureg)
|
|
|
648 if(tb&0x80)PULLWORD(ipcreg)
|
|
|
649 if(tracetrick&&tb==0xff) { /* Arrange fake FIRQ after next insn
|
|
|
650 for hardware tracing */
|
|
|
651 tracetrick=0;
|
|
|
652 irq=2;
|
|
|
653 attention=1;
|
|
|
654 goto flaginstr;
|
|
|
655 }
|
|
|
656 break;
|
|
|
657 case 0x36: /* PSHU*/ IMMBYTE(tb)
|
|
|
658 if(tb&0x80)PSHUWORD(ipcreg)
|
|
|
659 if(tb&0x40)PSHUWORD(isreg)
|
|
|
660 if(tb&0x20)PSHUWORD(iyreg)
|
|
|
661 if(tb&0x10)PSHUWORD(ixreg)
|
|
|
662 if(tb&0x08)PSHUBYTE(idpreg)
|
|
|
663 if(tb&0x04)PSHUBYTE(ibreg)
|
|
|
664 if(tb&0x02)PSHUBYTE(iareg)
|
|
|
665 if(tb&0x01)PSHUBYTE(iccreg) break;
|
|
|
666 case 0x37: /* PULU*/ IMMBYTE(tb)
|
|
|
667 if(tb&0x01)PULUBYTE(iccreg)
|
|
|
668 if(tb&0x02)PULUBYTE(iareg)
|
|
|
669 if(tb&0x04)PULUBYTE(ibreg)
|
|
|
670 if(tb&0x08)PULUBYTE(idpreg)
|
|
|
671 if(tb&0x10)PULUWORD(ixreg)
|
|
|
672 if(tb&0x20)PULUWORD(iyreg)
|
|
|
673 if(tb&0x40)PULUWORD(isreg)
|
|
|
674 if(tb&0x80)PULUWORD(ipcreg) break;
|
|
|
675 case 0x39: /* RTS*/ PULLWORD(ipcreg) break;
|
|
|
676 case 0x3A: /* ABX*/ ixreg+=ibreg; break;
|
|
13
|
677 case 0x3B: /* RTI*/ PULLBYTE(iccreg)
|
|
|
678 tb=iccreg&0x80;
|
|
0
|
679 if(tb)
|
|
|
680 {
|
|
|
681 PULLBYTE(iareg)
|
|
|
682 PULLBYTE(ibreg)
|
|
|
683 PULLBYTE(idpreg)
|
|
|
684 PULLWORD(ixreg)
|
|
|
685 PULLWORD(iyreg)
|
|
|
686 PULLWORD(iureg)
|
|
|
687 }
|
|
|
688 PULLWORD(ipcreg) break;
|
|
|
689 case 0x3C: /* CWAI*/ IMMBYTE(tb)
|
|
|
690 PUSHWORD(ipcreg)
|
|
|
691 PUSHWORD(iureg)
|
|
|
692 PUSHWORD(iyreg)
|
|
|
693 PUSHWORD(ixreg)
|
|
|
694 PUSHBYTE(idpreg)
|
|
|
695 PUSHBYTE(ibreg)
|
|
|
696 PUSHBYTE(iareg)
|
|
|
697 PUSHBYTE(iccreg)
|
|
|
698 iccreg&=tb;
|
|
|
699 iccreg|=0x80;
|
|
|
700 do usleep(USLEEP); /* Wait for IRQ */
|
|
|
701 while(!attention && !((irq==1&&!(iccreg&0x10))||(irq==2&&!(iccreg&0x040))));
|
|
|
702 if(irq==1)ipcreg=GETWORD(0xfff8);
|
|
|
703 else ipcreg=GETWORD(0xfff6);
|
|
|
704 irq=0;
|
|
|
705 if(!tracing)attention=0;
|
|
|
706 break;
|
|
|
707 case 0x3D: /* MUL*/ tw=iareg*ibreg; if(tw)CLZ else SEZ
|
|
|
708 if(tw&0x80) SEC else CLC SETDREG(tw) break;
|
|
|
709 case 0x3E: break; /*ILLEGAL*/
|
|
|
710 case 0x3F: /* SWI (SWI2 SWI3)*/ {
|
|
|
711 PUSHWORD(ipcreg)
|
|
|
712 PUSHWORD(iureg)
|
|
|
713 PUSHWORD(iyreg)
|
|
|
714 PUSHWORD(ixreg)
|
|
|
715 PUSHBYTE(idpreg)
|
|
|
716 PUSHBYTE(ibreg)
|
|
|
717 PUSHBYTE(iareg)
|
|
13
|
718 iccreg|=0x80;
|
|
0
|
719 PUSHBYTE(iccreg)
|
|
|
720 if(!iflag)iccreg|=0x50;
|
|
|
721 switch(iflag) {
|
|
|
722 case 0:ipcreg=GETWORD(0xfffa);break;
|
|
|
723 case 1:ipcreg=GETWORD(0xfff4);break;
|
|
|
724 case 2:ipcreg=GETWORD(0xfff2);break;
|
|
|
725 }
|
|
|
726 }break;
|
|
|
727 case 0x40: /*NEGA*/ tw=-iareg;SETSTATUS(0,iareg,tw)
|
|
|
728 iareg=tw;break;
|
|
|
729 case 0x41: break;/*ILLEGAL*/
|
|
|
730 case 0x42: break;/*ILLEGAL*/
|
|
|
731 case 0x43: /*COMA*/ tb=~iareg;SETNZ8(tb);SEC CLV
|
|
|
732 iareg=tb;break;
|
|
|
733 case 0x44: /*LSRA*/ tb=iareg;if(tb&0x01)SEC else CLC
|
|
|
734 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
735 iareg=tb;break;
|
|
|
736 case 0x45: break;/* ILLEGAL*/
|
|
|
737 case 0x46: /*RORA*/ tb=(iccreg&0x01)<<7;
|
|
|
738 if(iareg&0x01)SEC else CLC
|
|
|
739 iareg=(iareg>>1)+tb;SETNZ8(iareg)
|
|
|
740 break;
|
|
|
741 case 0x47: /*ASRA*/ tb=iareg;if(tb&0x01)SEC else CLC
|
|
|
742 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
743 if(tb&0x40)tb|=0x80;iareg=tb;SETNZ8(tb)
|
|
|
744 break;
|
|
|
745 case 0x48: /*ASLA*/ tw=iareg<<1;
|
|
|
746 SETSTATUS(iareg,iareg,tw)
|
|
|
747 iareg=tw;break;
|
|
|
748 case 0x49: /*ROLA*/ tb=iareg;tw=iccreg&0x01;
|
|
|
749 if(tb&0x80)SEC else CLC
|
|
|
750 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
751 tb=(tb<<1)+tw;SETNZ8(tb) iareg=tb;break;
|
|
|
752 case 0x4A: /*DECA*/ tb=iareg-1;if(tb==0x7F)SEV else CLV
|
|
|
753 SETNZ8(tb) iareg=tb;break;
|
|
|
754 case 0x4B: break; /*ILLEGAL*/
|
|
|
755 case 0x4C: /*INCA*/ tb=iareg+1;if(tb==0x80)SEV else CLV
|
|
|
756 SETNZ8(tb) iareg=tb;break;
|
|
|
757 case 0x4D: /*TSTA*/ SETNZ8(iareg) break;
|
|
|
758 case 0x4E: break; /*ILLEGAL*/
|
|
|
759 case 0x4F: /*CLRA*/ iareg=0;CLN CLV SEZ CLC break;
|
|
|
760 case 0x50: /*NEGB*/ tw=-ibreg;SETSTATUS(0,ibreg,tw)
|
|
|
761 ibreg=tw;break;
|
|
|
762 case 0x51: break;/*ILLEGAL*/
|
|
|
763 case 0x52: break;/*ILLEGAL*/
|
|
|
764 case 0x53: /*COMB*/ tb=~ibreg;SETNZ8(tb);SEC CLV
|
|
|
765 ibreg=tb;break;
|
|
|
766 case 0x54: /*LSRB*/ tb=ibreg;if(tb&0x01)SEC else CLC
|
|
|
767 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
768 ibreg=tb;break;
|
|
|
769 case 0x55: break;/* ILLEGAL*/
|
|
|
770 case 0x56: /*RORB*/ tb=(iccreg&0x01)<<7;
|
|
|
771 if(ibreg&0x01)SEC else CLC
|
|
|
772 ibreg=(ibreg>>1)+tb;SETNZ8(ibreg)
|
|
|
773 break;
|
|
|
774 case 0x57: /*ASRB*/ tb=ibreg;if(tb&0x01)SEC else CLC
|
|
|
775 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
776 if(tb&0x40)tb|=0x80;ibreg=tb;SETNZ8(tb)
|
|
|
777 break;
|
|
|
778 case 0x58: /*ASLB*/ tw=ibreg<<1;
|
|
|
779 SETSTATUS(ibreg,ibreg,tw)
|
|
|
780 ibreg=tw;break;
|
|
|
781 case 0x59: /*ROLB*/ tb=ibreg;tw=iccreg&0x01;
|
|
|
782 if(tb&0x80)SEC else CLC
|
|
|
783 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
784 tb=(tb<<1)+tw;SETNZ8(tb) ibreg=tb;break;
|
|
|
785 case 0x5A: /*DECB*/ tb=ibreg-1;if(tb==0x7F)SEV else CLV
|
|
|
786 SETNZ8(tb) ibreg=tb;break;
|
|
|
787 case 0x5B: break; /*ILLEGAL*/
|
|
|
788 case 0x5C: /*INCB*/ tb=ibreg+1;if(tb==0x80)SEV else CLV
|
|
|
789 SETNZ8(tb) ibreg=tb;break;
|
|
|
790 case 0x5D: /*TSTB*/ SETNZ8(ibreg) break;
|
|
|
791 case 0x5E: break; /*ILLEGAL*/
|
|
|
792 case 0x5F: /*CLRB*/ ibreg=0;CLN CLV SEZ CLC break;
|
|
4
|
793 case 0x60: /*NEG indexed*/ tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw)
|
|
0
|
794 SETBYTE(eaddr,tw)break;
|
|
|
795 case 0x61: break;/*ILLEGAL*/
|
|
|
796 case 0x62: break;/*ILLEGAL*/
|
|
4
|
797 case 0x63: /*COM indexed*/ tb=~mem(eaddr);SETNZ8(tb);SEC CLV
|
|
0
|
798 SETBYTE(eaddr,tb)break;
|
|
4
|
799 case 0x64: /*LSR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC
|
|
0
|
800 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
801 SETBYTE(eaddr,tb)break;
|
|
|
802 case 0x65: break;/* ILLEGAL*/
|
|
|
803 case 0x66: /*ROR indexed*/ tb=(iccreg&0x01)<<7;
|
|
4
|
804 if(mem(eaddr)&0x01)SEC else CLC
|
|
|
805 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw)
|
|
0
|
806 SETBYTE(eaddr,tw)
|
|
|
807 break;
|
|
4
|
808 case 0x67: /*ASR indexed*/ tb=mem(eaddr);if(tb&0x01)SEC else CLC
|
|
0
|
809 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
810 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
|
|
|
811 break;
|
|
4
|
812 case 0x68: /*ASL indexed*/ tw=mem(eaddr)<<1;
|
|
|
813 SETSTATUS(mem(eaddr),mem(eaddr),tw)
|
|
0
|
814 SETBYTE(eaddr,tw)break;
|
|
4
|
815 case 0x69: /*ROL indexed*/ tb=mem(eaddr);tw=iccreg&0x01;
|
|
0
|
816 if(tb&0x80)SEC else CLC
|
|
|
817 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
818 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
4
|
819 case 0x6A: /*DEC indexed*/ tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV
|
|
0
|
820 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
821 case 0x6B: break; /*ILLEGAL*/
|
|
4
|
822 case 0x6C: /*INC indexed*/ tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV
|
|
0
|
823 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
4
|
824 case 0x6D: /*TST indexed*/ tb=mem(eaddr);SETNZ8(tb) break;
|
|
0
|
825 case 0x6E: /*JMP indexed*/ ipcreg=eaddr;break;
|
|
|
826 case 0x6F: /*CLR indexed*/ SETBYTE(eaddr,0)CLN CLV SEZ CLC break;
|
|
4
|
827 case 0x70: /*NEG ext*/ EXTENDED tw=-mem(eaddr);SETSTATUS(0,mem(eaddr),tw)
|
|
0
|
828 SETBYTE(eaddr,tw)break;
|
|
|
829 case 0x71: break;/*ILLEGAL*/
|
|
|
830 case 0x72: break;/*ILLEGAL*/
|
|
4
|
831 case 0x73: /*COM ext*/ EXTENDED tb=~mem(eaddr);SETNZ8(tb);SEC CLV
|
|
0
|
832 SETBYTE(eaddr,tb)break;
|
|
4
|
833 case 0x74: /*LSR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC
|
|
0
|
834 if(tb&0x10)SEH else CLH tb>>=1;SETNZ8(tb)
|
|
|
835 SETBYTE(eaddr,tb)break;
|
|
|
836 case 0x75: break;/* ILLEGAL*/
|
|
|
837 case 0x76: /*ROR ext*/ EXTENDED tb=(iccreg&0x01)<<7;
|
|
4
|
838 if(mem(eaddr)&0x01)SEC else CLC
|
|
|
839 tw=(mem(eaddr)>>1)+tb;SETNZ8(tw)
|
|
0
|
840 SETBYTE(eaddr,tw)
|
|
|
841 break;
|
|
4
|
842 case 0x77: /*ASR ext*/ EXTENDED tb=mem(eaddr);if(tb&0x01)SEC else CLC
|
|
0
|
843 if(tb&0x10)SEH else CLH tb>>=1;
|
|
|
844 if(tb&0x40)tb|=0x80;SETBYTE(eaddr,tb)SETNZ8(tb)
|
|
|
845 break;
|
|
4
|
846 case 0x78: /*ASL ext*/ EXTENDED tw=mem(eaddr)<<1;
|
|
|
847 SETSTATUS(mem(eaddr),mem(eaddr),tw)
|
|
0
|
848 SETBYTE(eaddr,tw)break;
|
|
4
|
849 case 0x79: /*ROL ext*/ EXTENDED tb=mem(eaddr);tw=iccreg&0x01;
|
|
0
|
850 if(tb&0x80)SEC else CLC
|
|
|
851 if((tb&0x80)^((tb<<1)&0x80))SEV else CLV
|
|
|
852 tb=(tb<<1)+tw;SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
4
|
853 case 0x7A: /*DEC ext*/ EXTENDED tb=mem(eaddr)-1;if(tb==0x7F)SEV else CLV
|
|
0
|
854 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
|
855 case 0x7B: break; /*ILLEGAL*/
|
|
4
|
856 case 0x7C: /*INC ext*/ EXTENDED tb=mem(eaddr)+1;if(tb==0x80)SEV else CLV
|
|
0
|
857 SETNZ8(tb) SETBYTE(eaddr,tb)break;
|
|
4
|
858 case 0x7D: /*TST ext*/ EXTENDED tb=mem(eaddr);SETNZ8(tb) break;
|
|
0
|
859 case 0x7E: /*JMP ext*/ EXTENDED ipcreg=eaddr;break;
|
|
|
860 case 0x7F: /*CLR ext*/ EXTENDED SETBYTE(eaddr,0)CLN CLV SEZ CLC break;
|
|
4
|
861 case 0x80: /*SUBA immediate*/ IMM8 tw=iareg-mem(eaddr);
|
|
|
862 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
863 iareg=tw;break;
|
|
4
|
864 case 0x81: /*CMPA immediate*/ IMM8 tw=iareg-mem(eaddr);
|
|
|
865 SETSTATUS(iareg,mem(eaddr),tw) break;
|
|
|
866 case 0x82: /*SBCA immediate*/ IMM8 tw=iareg-mem(eaddr)-(iccreg&0x01);
|
|
|
867 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
868 iareg=tw;break;
|
|
|
869 case 0x83: /*SUBD (CMPD CMPU) immediate*/ IMM16
|
|
|
870 {unsigned long res,dreg,breg;
|
|
|
871 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
872 breg=GETWORD(eaddr);
|
|
|
873 res=dreg-breg;
|
|
|
874 SETSTATUSD(dreg,breg,res)
|
|
|
875 if(iflag==0) SETDREG(res)
|
|
|
876 }break;
|
|
4
|
877 case 0x84: /*ANDA immediate*/ IMM8 iareg=iareg&mem(eaddr);SETNZ8(iareg)
|
|
0
|
878 CLV break;
|
|
4
|
879 case 0x85: /*BITA immediate*/ IMM8 tb=iareg&mem(eaddr);SETNZ8(tb)
|
|
0
|
880 CLV break;
|
|
|
881 case 0x86: /*LDA immediate*/ IMM8 LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
882 break;
|
|
|
883 case 0x87: /*STA immediate (for the sake of orthogonality) */ IMM8
|
|
|
884 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
4
|
885 case 0x88: /*EORA immediate*/ IMM8 iareg=iareg^mem(eaddr);SETNZ8(iareg)
|
|
0
|
886 CLV break;
|
|
4
|
887 case 0x89: /*ADCA immediate*/ IMM8 tw=iareg+mem(eaddr)+(iccreg&0x01);
|
|
|
888 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
889 iareg=tw;break;
|
|
4
|
890 case 0x8A: /*ORA immediate*/ IMM8 iareg=iareg|mem(eaddr);SETNZ8(iareg)
|
|
0
|
891 CLV break;
|
|
4
|
892 case 0x8B: /*ADDA immediate*/ IMM8 tw=iareg+mem(eaddr);
|
|
|
893 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
894 iareg=tw;break;
|
|
|
895 case 0x8C: /*CMPX (CMPY CMPS) immediate */ IMM16
|
|
|
896 {unsigned long dreg,breg,res;
|
|
|
897 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
898 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
899 res=dreg-breg;
|
|
|
900 SETSTATUSD(dreg,breg,res)
|
|
|
901 }break;
|
|
|
902 case 0x8D: /*BSR */ IMMBYTE(tb) PUSHWORD(ipcreg) ipcreg+=SIGNED(tb);
|
|
|
903 break;
|
|
|
904 case 0x8E: /* LDX (LDY) immediate */ IMM16 tw=GETWORD(eaddr);
|
|
|
905 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
906 iyreg=tw;break;
|
|
|
907 case 0x8F: /* STX (STY) immediate (orthogonality) */ IMM16
|
|
|
908 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
909 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
910 case 0x90: /*SUBA direct*/ DIRECT tw=iareg-mem(eaddr);
|
|
|
911 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
912 iareg=tw;break;
|
|
4
|
913 case 0x91: /*CMPA direct*/ DIRECT tw=iareg-mem(eaddr);
|
|
|
914 SETSTATUS(iareg,mem(eaddr),tw) break;
|
|
|
915 case 0x92: /*SBCA direct*/ DIRECT tw=iareg-mem(eaddr)-(iccreg&0x01);
|
|
|
916 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
917 iareg=tw;break;
|
|
|
918 case 0x93: /*SUBD (CMPD CMPU) direct*/ DIRECT
|
|
|
919 {unsigned long res,dreg,breg;
|
|
|
920 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
921 breg=GETWORD(eaddr);
|
|
|
922 res=dreg-breg;
|
|
|
923 SETSTATUSD(dreg,breg,res)
|
|
|
924 if(iflag==0) SETDREG(res)
|
|
|
925 }break;
|
|
4
|
926 case 0x94: /*ANDA direct*/ DIRECT iareg=iareg&mem(eaddr);SETNZ8(iareg)
|
|
0
|
927 CLV break;
|
|
4
|
928 case 0x95: /*BITA direct*/ DIRECT tb=iareg&mem(eaddr);SETNZ8(tb)
|
|
0
|
929 CLV break;
|
|
|
930 case 0x96: /*LDA direct*/ DIRECT LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
931 break;
|
|
|
932 case 0x97: /*STA direct */ DIRECT
|
|
|
933 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
4
|
934 case 0x98: /*EORA direct*/ DIRECT iareg=iareg^mem(eaddr);SETNZ8(iareg)
|
|
0
|
935 CLV break;
|
|
4
|
936 case 0x99: /*ADCA direct*/ DIRECT tw=iareg+mem(eaddr)+(iccreg&0x01);
|
|
|
937 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
938 iareg=tw;break;
|
|
4
|
939 case 0x9A: /*ORA direct*/ DIRECT iareg=iareg|mem(eaddr);SETNZ8(iareg)
|
|
0
|
940 CLV break;
|
|
4
|
941 case 0x9B: /*ADDA direct*/ DIRECT tw=iareg+mem(eaddr);
|
|
|
942 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
943 iareg=tw;break;
|
|
|
944 case 0x9C: /*CMPX (CMPY CMPS) direct */ DIRECT
|
|
|
945 {unsigned long dreg,breg,res;
|
|
|
946 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
947 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
948 res=dreg-breg;
|
|
|
949 SETSTATUSD(dreg,breg,res)
|
|
|
950 }break;
|
|
|
951 case 0x9D: /*JSR direct */ DIRECT PUSHWORD(ipcreg) ipcreg=eaddr;
|
|
|
952 break;
|
|
|
953 case 0x9E: /* LDX (LDY) direct */ DIRECT tw=GETWORD(eaddr);
|
|
|
954 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
955 iyreg=tw;break;
|
|
|
956 case 0x9F: /* STX (STY) direct */ DIRECT
|
|
|
957 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
958 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
959 case 0xA0: /*SUBA indexed*/ tw=iareg-mem(eaddr);
|
|
|
960 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
961 iareg=tw;break;
|
|
4
|
962 case 0xA1: /*CMPA indexed*/ tw=iareg-mem(eaddr);
|
|
|
963 SETSTATUS(iareg,mem(eaddr),tw) break;
|
|
|
964 case 0xA2: /*SBCA indexed*/ tw=iareg-mem(eaddr)-(iccreg&0x01);
|
|
|
965 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
966 iareg=tw;break;
|
|
|
967 case 0xA3: /*SUBD (CMPD CMPU) indexed*/
|
|
|
968 {unsigned long res,dreg,breg;
|
|
|
969 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
970 breg=GETWORD(eaddr);
|
|
|
971 res=dreg-breg;
|
|
|
972 SETSTATUSD(dreg,breg,res)
|
|
|
973 if(iflag==0) SETDREG(res)
|
|
|
974 }break;
|
|
4
|
975 case 0xA4: /*ANDA indexed*/ iareg=iareg&mem(eaddr);SETNZ8(iareg)
|
|
0
|
976 CLV break;
|
|
4
|
977 case 0xA5: /*BITA indexed*/ tb=iareg&mem(eaddr);SETNZ8(tb)
|
|
0
|
978 CLV break;
|
|
|
979 case 0xA6: /*LDA indexed*/ LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
980 break;
|
|
|
981 case 0xA7: /*STA indexed */
|
|
|
982 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
4
|
983 case 0xA8: /*EORA indexed*/ iareg=iareg^mem(eaddr);SETNZ8(iareg)
|
|
0
|
984 CLV break;
|
|
4
|
985 case 0xA9: /*ADCA indexed*/ tw=iareg+mem(eaddr)+(iccreg&0x01);
|
|
|
986 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
987 iareg=tw;break;
|
|
4
|
988 case 0xAA: /*ORA indexed*/ iareg=iareg|mem(eaddr);SETNZ8(iareg)
|
|
0
|
989 CLV break;
|
|
4
|
990 case 0xAB: /*ADDA indexed*/ tw=iareg+mem(eaddr);
|
|
|
991 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
992 iareg=tw;break;
|
|
|
993 case 0xAC: /*CMPX (CMPY CMPS) indexed */
|
|
|
994 {unsigned long dreg,breg,res;
|
|
|
995 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
996 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
997 res=dreg-breg;
|
|
|
998 SETSTATUSD(dreg,breg,res)
|
|
|
999 }break;
|
|
|
1000 case 0xAD: /*JSR indexed */ PUSHWORD(ipcreg) ipcreg=eaddr;
|
|
|
1001 break;
|
|
|
1002 case 0xAE: /* LDX (LDY) indexed */ tw=GETWORD(eaddr);
|
|
|
1003 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
1004 iyreg=tw;break;
|
|
|
1005 case 0xAF: /* STX (STY) indexed */
|
|
|
1006 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
1007 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
1008 case 0xB0: /*SUBA ext*/ EXTENDED tw=iareg-mem(eaddr);
|
|
|
1009 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
1010 iareg=tw;break;
|
|
4
|
1011 case 0xB1: /*CMPA ext*/ EXTENDED tw=iareg-mem(eaddr);
|
|
|
1012 SETSTATUS(iareg,mem(eaddr),tw) break;
|
|
|
1013 case 0xB2: /*SBCA ext*/ EXTENDED tw=iareg-mem(eaddr)-(iccreg&0x01);
|
|
|
1014 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
1015 iareg=tw;break;
|
|
|
1016 case 0xB3: /*SUBD (CMPD CMPU) ext*/ EXTENDED
|
|
|
1017 {unsigned long res,dreg,breg;
|
|
|
1018 if(iflag==2)dreg=iureg;else dreg=GETDREG;
|
|
|
1019 breg=GETWORD(eaddr);
|
|
|
1020 res=dreg-breg;
|
|
|
1021 SETSTATUSD(dreg,breg,res)
|
|
|
1022 if(iflag==0) SETDREG(res)
|
|
|
1023 }break;
|
|
4
|
1024 case 0xB4: /*ANDA ext*/ EXTENDED iareg=iareg&mem(eaddr);SETNZ8(iareg)
|
|
0
|
1025 CLV break;
|
|
4
|
1026 case 0xB5: /*BITA ext*/ EXTENDED tb=iareg&mem(eaddr);SETNZ8(tb)
|
|
0
|
1027 CLV break;
|
|
|
1028 case 0xB6: /*LDA ext*/ EXTENDED LOADAC(iareg) CLV SETNZ8(iareg)
|
|
|
1029 break;
|
|
|
1030 case 0xB7: /*STA ext */ EXTENDED
|
|
|
1031 SETNZ8(iareg) CLV STOREAC(iareg) break;
|
|
4
|
1032 case 0xB8: /*EORA ext*/ EXTENDED iareg=iareg^mem(eaddr);SETNZ8(iareg)
|
|
0
|
1033 CLV break;
|
|
4
|
1034 case 0xB9: /*ADCA ext*/ EXTENDED tw=iareg+mem(eaddr)+(iccreg&0x01);
|
|
|
1035 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
1036 iareg=tw;break;
|
|
4
|
1037 case 0xBA: /*ORA ext*/ EXTENDED iareg=iareg|mem(eaddr);SETNZ8(iareg)
|
|
0
|
1038 CLV break;
|
|
4
|
1039 case 0xBB: /*ADDA ext*/ EXTENDED tw=iareg+mem(eaddr);
|
|
|
1040 SETSTATUS(iareg,mem(eaddr),tw)
|
|
0
|
1041 iareg=tw;break;
|
|
|
1042 case 0xBC: /*CMPX (CMPY CMPS) ext */ EXTENDED
|
|
|
1043 {unsigned long dreg,breg,res;
|
|
|
1044 if(iflag==0)dreg=ixreg;else if(iflag==1)
|
|
|
1045 dreg=iyreg;else dreg=isreg;breg=GETWORD(eaddr);
|
|
|
1046 res=dreg-breg;
|
|
|
1047 SETSTATUSD(dreg,breg,res)
|
|
|
1048 }break;
|
|
|
1049 case 0xBD: /*JSR ext */ EXTENDED PUSHWORD(ipcreg) ipcreg=eaddr;
|
|
|
1050 break;
|
|
|
1051 case 0xBE: /* LDX (LDY) ext */ EXTENDED tw=GETWORD(eaddr);
|
|
|
1052 CLV SETNZ16(tw) if(!iflag)ixreg=tw; else
|
|
|
1053 iyreg=tw;break;
|
|
|
1054 case 0xBF: /* STX (STY) ext */ EXTENDED
|
|
|
1055 if(!iflag) tw=ixreg; else tw=iyreg;
|
|
|
1056 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
1057 case 0xC0: /*SUBB immediate*/ IMM8 tw=ibreg-mem(eaddr);
|
|
|
1058 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1059 ibreg=tw;break;
|
|
4
|
1060 case 0xC1: /*CMPB immediate*/ IMM8 tw=ibreg-mem(eaddr);
|
|
|
1061 SETSTATUS(ibreg,mem(eaddr),tw) break;
|
|
|
1062 case 0xC2: /*SBCB immediate*/ IMM8 tw=ibreg-mem(eaddr)-(iccreg&0x01);
|
|
|
1063 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1064 ibreg=tw;break;
|
|
|
1065 case 0xC3: /*ADDD immediate*/ IMM16
|
|
|
1066 {unsigned long res,dreg,breg;
|
|
|
1067 dreg=GETDREG;
|
|
|
1068 breg=GETWORD(eaddr);
|
|
|
1069 res=dreg+breg;
|
|
|
1070 SETSTATUSD(dreg,breg,res)
|
|
|
1071 SETDREG(res)
|
|
|
1072 }break;
|
|
4
|
1073 case 0xC4: /*ANDB immediate*/ IMM8 ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1074 CLV break;
|
|
4
|
1075 case 0xC5: /*BITB immediate*/ IMM8 tb=ibreg&mem(eaddr);SETNZ8(tb)
|
|
0
|
1076 CLV break;
|
|
|
1077 case 0xC6: /*LDB immediate*/ IMM8 LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1078 break;
|
|
|
1079 case 0xC7: /*STB immediate (for the sake of orthogonality) */ IMM8
|
|
|
1080 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
4
|
1081 case 0xC8: /*EORB immediate*/ IMM8 ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1082 CLV break;
|
|
4
|
1083 case 0xC9: /*ADCB immediate*/ IMM8 tw=ibreg+mem(eaddr)+(iccreg&0x01);
|
|
|
1084 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1085 ibreg=tw;break;
|
|
4
|
1086 case 0xCA: /*ORB immediate*/ IMM8 ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1087 CLV break;
|
|
4
|
1088 case 0xCB: /*ADDB immediate*/ IMM8 tw=ibreg+mem(eaddr);
|
|
|
1089 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1090 ibreg=tw;break;
|
|
|
1091 case 0xCC: /*LDD immediate */ IMM16 tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1092 CLV SETDREG(tw) break;
|
|
|
1093 case 0xCD: /*STD immediate (orthogonality) */ IMM16
|
|
|
1094 tw=GETDREG; SETNZ16(tw) CLV
|
|
|
1095 SETWORD(eaddr,tw) break;
|
|
|
1096 case 0xCE: /* LDU (LDS) immediate */ IMM16 tw=GETWORD(eaddr);
|
|
|
1097 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1098 isreg=tw;break;
|
|
|
1099 case 0xCF: /* STU (STS) immediate (orthogonality) */ IMM16
|
|
|
1100 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1101 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
1102 case 0xD0: /*SUBB direct*/ DIRECT tw=ibreg-mem(eaddr);
|
|
|
1103 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1104 ibreg=tw;break;
|
|
4
|
1105 case 0xD1: /*CMPB direct*/ DIRECT tw=ibreg-mem(eaddr);
|
|
|
1106 SETSTATUS(ibreg,mem(eaddr),tw) break;
|
|
|
1107 case 0xD2: /*SBCB direct*/ DIRECT tw=ibreg-mem(eaddr)-(iccreg&0x01);
|
|
|
1108 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1109 ibreg=tw;break;
|
|
|
1110 case 0xD3: /*ADDD direct*/ DIRECT
|
|
|
1111 {unsigned long res,dreg,breg;
|
|
|
1112 dreg=GETDREG;
|
|
|
1113 breg=GETWORD(eaddr);
|
|
|
1114 res=dreg+breg;
|
|
|
1115 SETSTATUSD(dreg,breg,res)
|
|
|
1116 SETDREG(res)
|
|
|
1117 }break;
|
|
4
|
1118 case 0xD4: /*ANDB direct*/ DIRECT ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1119 CLV break;
|
|
4
|
1120 case 0xD5: /*BITB direct*/ DIRECT tb=ibreg&mem(eaddr);SETNZ8(tb)
|
|
0
|
1121 CLV break;
|
|
|
1122 case 0xD6: /*LDB direct*/ DIRECT LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1123 break;
|
|
|
1124 case 0xD7: /*STB direct */ DIRECT
|
|
|
1125 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
4
|
1126 case 0xD8: /*EORB direct*/ DIRECT ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1127 CLV break;
|
|
4
|
1128 case 0xD9: /*ADCB direct*/ DIRECT tw=ibreg+mem(eaddr)+(iccreg&0x01);
|
|
|
1129 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1130 ibreg=tw;break;
|
|
4
|
1131 case 0xDA: /*ORB direct*/ DIRECT ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1132 CLV break;
|
|
4
|
1133 case 0xDB: /*ADDB direct*/ DIRECT tw=ibreg+mem(eaddr);
|
|
|
1134 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1135 ibreg=tw;break;
|
|
|
1136 case 0xDC: /*LDD direct */ DIRECT tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1137 CLV SETDREG(tw) break;
|
|
|
1138 case 0xDD: /*STD direct */ DIRECT
|
|
|
1139 tw=GETDREG; SETNZ16(tw) CLV
|
|
11
|
1140 #ifdef USE_MMU
|
|
|
1141 STOREAC((tw>>8)&0x0ff); eaddr++;
|
|
|
1142 STOREAC(tw&0x0ff); break;
|
|
|
1143 #else
|
|
0
|
1144 SETWORD(eaddr,tw) break;
|
|
11
|
1145 #endif
|
|
0
|
1146 case 0xDE: /* LDU (LDS) direct */ DIRECT tw=GETWORD(eaddr);
|
|
|
1147 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1148 isreg=tw;break;
|
|
|
1149 case 0xDF: /* STU (STS) direct */ DIRECT
|
|
|
1150 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1151 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
1152 case 0xE0: /*SUBB indexed*/ tw=ibreg-mem(eaddr);
|
|
|
1153 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1154 ibreg=tw;break;
|
|
4
|
1155 case 0xE1: /*CMPB indexed*/ tw=ibreg-mem(eaddr);
|
|
|
1156 SETSTATUS(ibreg,mem(eaddr),tw) break;
|
|
|
1157 case 0xE2: /*SBCB indexed*/ tw=ibreg-mem(eaddr)-(iccreg&0x01);
|
|
|
1158 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1159 ibreg=tw;break;
|
|
|
1160 case 0xE3: /*ADDD indexed*/
|
|
|
1161 {unsigned long res,dreg,breg;
|
|
|
1162 dreg=GETDREG;
|
|
|
1163 breg=GETWORD(eaddr);
|
|
|
1164 res=dreg+breg;
|
|
|
1165 SETSTATUSD(dreg,breg,res)
|
|
|
1166 SETDREG(res)
|
|
|
1167 }break;
|
|
4
|
1168 case 0xE4: /*ANDB indexed*/ ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1169 CLV break;
|
|
4
|
1170 case 0xE5: /*BITB indexed*/ tb=ibreg&mem(eaddr);SETNZ8(tb)
|
|
0
|
1171 CLV break;
|
|
|
1172 case 0xE6: /*LDB indexed*/ LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1173 break;
|
|
|
1174 case 0xE7: /*STB indexed */
|
|
|
1175 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
4
|
1176 case 0xE8: /*EORB indexed*/ ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1177 CLV break;
|
|
4
|
1178 case 0xE9: /*ADCB indexed*/ tw=ibreg+mem(eaddr)+(iccreg&0x01);
|
|
|
1179 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1180 ibreg=tw;break;
|
|
4
|
1181 case 0xEA: /*ORB indexed*/ ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1182 CLV break;
|
|
4
|
1183 case 0xEB: /*ADDB indexed*/ tw=ibreg+mem(eaddr);
|
|
|
1184 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1185 ibreg=tw;break;
|
|
|
1186 case 0xEC: /*LDD indexed */ tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1187 CLV SETDREG(tw) break;
|
|
|
1188 case 0xED: /*STD indexed */
|
|
|
1189 tw=GETDREG; SETNZ16(tw) CLV
|
|
10
|
1190 #ifdef USE_MMU
|
|
11
|
1191 STOREAC((tw>>8)&0x0ff); eaddr++;
|
|
10
|
1192 STOREAC(tw&0x0ff);
|
|
|
1193 break;
|
|
|
1194 #else
|
|
0
|
1195 SETWORD(eaddr,tw) break;
|
|
10
|
1196 #endif
|
|
0
|
1197 case 0xEE: /* LDU (LDS) indexed */ tw=GETWORD(eaddr);
|
|
|
1198 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1199 isreg=tw;break;
|
|
|
1200 case 0xEF: /* STU (STS) indexed */
|
|
|
1201 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1202 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
4
|
1203 case 0xF0: /*SUBB ext*/ EXTENDED tw=ibreg-mem(eaddr);
|
|
|
1204 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1205 ibreg=tw;break;
|
|
4
|
1206 case 0xF1: /*CMPB ext*/ EXTENDED tw=ibreg-mem(eaddr);
|
|
|
1207 SETSTATUS(ibreg,mem(eaddr),tw) break;
|
|
|
1208 case 0xF2: /*SBCB ext*/ EXTENDED tw=ibreg-mem(eaddr)-(iccreg&0x01);
|
|
|
1209 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1210 ibreg=tw;break;
|
|
|
1211 case 0xF3: /*ADDD ext*/ EXTENDED
|
|
|
1212 {unsigned long res,dreg,breg;
|
|
|
1213 dreg=GETDREG;
|
|
|
1214 breg=GETWORD(eaddr);
|
|
|
1215 res=dreg+breg;
|
|
|
1216 SETSTATUSD(dreg,breg,res)
|
|
|
1217 SETDREG(res)
|
|
|
1218 }break;
|
|
4
|
1219 case 0xF4: /*ANDB ext*/ EXTENDED ibreg=ibreg&mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1220 CLV break;
|
|
4
|
1221 case 0xF5: /*BITB ext*/ EXTENDED tb=ibreg&mem(eaddr);SETNZ8(tb)
|
|
0
|
1222 CLV break;
|
|
|
1223 case 0xF6: /*LDB ext*/ EXTENDED LOADAC(ibreg) CLV SETNZ8(ibreg)
|
|
|
1224 break;
|
|
|
1225 case 0xF7: /*STB ext */ EXTENDED
|
|
|
1226 SETNZ8(ibreg) CLV STOREAC(ibreg) break;
|
|
4
|
1227 case 0xF8: /*EORB ext*/ EXTENDED ibreg=ibreg^mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1228 CLV break;
|
|
4
|
1229 case 0xF9: /*ADCB ext*/ EXTENDED tw=ibreg+mem(eaddr)+(iccreg&0x01);
|
|
|
1230 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1231 ibreg=tw;break;
|
|
4
|
1232 case 0xFA: /*ORB ext*/ EXTENDED ibreg=ibreg|mem(eaddr);SETNZ8(ibreg)
|
|
0
|
1233 CLV break;
|
|
4
|
1234 case 0xFB: /*ADDB ext*/ EXTENDED tw=ibreg+mem(eaddr);
|
|
|
1235 SETSTATUS(ibreg,mem(eaddr),tw)
|
|
0
|
1236 ibreg=tw;break;
|
|
|
1237 case 0xFC: /*LDD ext */ EXTENDED tw=GETWORD(eaddr);SETNZ16(tw)
|
|
|
1238 CLV SETDREG(tw) break;
|
|
|
1239 case 0xFD: /*STD ext */ EXTENDED
|
|
|
1240 tw=GETDREG; SETNZ16(tw) CLV
|
|
10
|
1241 #ifdef USE_MMU
|
|
11
|
1242 STOREAC((tw>>8)&0x0ff); eaddr++;
|
|
10
|
1243 STOREAC(tw&0x0ff);
|
|
|
1244 break;
|
|
|
1245 #else
|
|
0
|
1246 SETWORD(eaddr,tw) break;
|
|
10
|
1247 #endif
|
|
0
|
1248 case 0xFE: /* LDU (LDS) ext */ EXTENDED tw=GETWORD(eaddr);
|
|
|
1249 CLV SETNZ16(tw) if(!iflag)iureg=tw; else
|
|
|
1250 isreg=tw;break;
|
|
|
1251 case 0xFF: /* STU (STS) ext */ EXTENDED
|
|
|
1252 if(!iflag) tw=iureg; else tw=isreg;
|
|
|
1253 CLV SETNZ16(tw) SETWORD(eaddr,tw) break;
|
|
|
1254
|
|
|
1255
|
|
|
1256 }
|
|
|
1257 }
|
|
|
1258 }
|
|
|
1259
|
