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annotate test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
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1 ; RUN: llc -march=amdgcn -mcpu=SI -o - %s | FileCheck %s
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2 ; Don't crash when the use of an undefined value is only detected by the
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3 ; register coalescer because it is hidden with subregister insert/extract.
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4 target triple="amdgcn--"
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5
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6 ; CHECK-LABEL: foobar:
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7 ; CHECK: s_load_dword s2, s[0:1], 0x9
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8 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
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9 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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10 ; CHECK: v_mbcnt_lo_u32_b32_e64
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11 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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12 ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
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13 ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
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14 ; BB0_1:
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15 ; CHECK: s_load_dword s0, s[0:1], 0xa
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16 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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17 ; BB0_2:
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18 ; CHECK: s_or_b64 exec, exec, s[2:3]
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19 ; CHECK-NEXT: s_mov_b32 s7, 0xf000
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20 ; CHECK-NEXT: s_mov_b32 s6, -1
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21 ; CHECK-NEXT: buffer_store_dword v1, off, s[4:7], 0
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22 ; CHECK-NEXT: s_endpgm
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23 define void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind {
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24 entry:
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25 %v0 = insertelement <4 x float> undef, float %a0, i32 0
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26 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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27 %cnd = icmp eq i32 %tid, 0
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28 br i1 %cnd, label %ift, label %ife
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30 ift:
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31 %v1 = insertelement <4 x float> undef, float %a1, i32 0
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32 br label %ife
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33
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34 ife:
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35 %val = phi <4 x float> [ %v1, %ift ], [ %v0, %entry ]
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36 %v2 = extractelement <4 x float> %val, i32 1
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37 store float %v2, float addrspace(1)* %out, align 4
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38 ret void
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39 }
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41 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
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42
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43 attributes #0 = { nounwind readnone }