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annotate test/CodeGen/AArch64/adc.ll @ 77:54457678186b

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LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
parents 95c75e76d11b
children
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77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
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2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
0
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3
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4 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
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5 ; CHECK-LABEL: test_simple:
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6
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7 %valadd = add i128 %a, %b
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8 ; CHECK-LE: adds [[ADDLO:x[0-9]+]], x0, x2
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9 ; CHECK-LE-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
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10 ; CHECK-BE: adds [[ADDLO:x[0-9]+]], x1, x3
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11 ; CHECK-BE-NEXT: adcs [[ADDHI:x[0-9]+]], x0, x2
0
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12
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13 %valsub = sub i128 %valadd, %c
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14 ; CHECK-LE: subs x0, [[ADDLO]], x4
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15 ; CHECK-LE: sbcs x1, [[ADDHI]], x5
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16 ; CHECK-BE: subs x1, [[ADDLO]], x5
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17 ; CHECK-BE: sbcs x0, [[ADDHI]], x4
0
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18
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19 ret i128 %valsub
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20 ; CHECK: ret
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21 }
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22
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23 define i128 @test_imm(i128 %a) {
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24 ; CHECK-LABEL: test_imm:
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25
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26 %val = add i128 %a, 12
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27 ; CHECK-LE: adds x0, x0, #12
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28 ; CHECK-LE: adcs x1, x1, {{x[0-9]|xzr}}
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29 ; CHECK-BE: adds x1, x1, #12
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30 ; CHECK-BE: adcs x0, x0, {{x[0-9]|xzr}}
0
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31
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32 ret i128 %val
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33 ; CHECK: ret
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34 }
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35
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36 define i128 @test_shifted(i128 %a, i128 %b) {
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37 ; CHECK-LABEL: test_shifted:
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38
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39 %rhs = shl i128 %b, 45
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40
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41 %val = add i128 %a, %rhs
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42 ; CHECK-LE: adds x0, x0, x2, lsl #45
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43 ; CHECK-LE: adcs x1, x1, {{x[0-9]}}
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44 ; CHECK-BE: adds x1, x1, x3, lsl #45
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45 ; CHECK-BE: adcs x0, x0, {{x[0-9]}}
0
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46
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47 ret i128 %val
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48 ; CHECK: ret
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49 }
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50
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51 define i128 @test_extended(i128 %a, i16 %b) {
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52 ; CHECK-LABEL: test_extended:
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53
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54 %ext = sext i16 %b to i128
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55 %rhs = shl i128 %ext, 3
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56
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57 %val = add i128 %a, %rhs
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58 ; CHECK-LE: adds x0, x0, w2, sxth #3
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59 ; CHECK-LE: adcs x1, x1, {{x[0-9]}}
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60 ; CHECK-BE: adds x1, x1, w2, sxth #3
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61 ; CHECK-BE: adcs x0, x0, {{x[0-9]}}
0
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62
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63 ret i128 %val
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64 ; CHECK: ret
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65 }