annotate test/CodeGen/AArch64/arm64-sminv.ll @ 77:54457678186b

LLVM 3.6
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Mon, 08 Sep 2014 22:06:00 +0900
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children afa8332a0e37
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54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
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2
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3 define signext i8 @test_vminv_s8(<8 x i8> %a1) {
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4 ; CHECK: test_vminv_s8
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5 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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7 ; CHECK-NEXT: ret
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8 entry:
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9 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
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10 %0 = trunc i32 %vminv.i to i8
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11 ret i8 %0
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12 }
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13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 define signext i16 @test_vminv_s16(<4 x i16> %a1) {
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15 ; CHECK: test_vminv_s16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
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17 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 ; CHECK-NEXT: ret
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19 entry:
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20 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
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21 %0 = trunc i32 %vminv.i to i16
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22 ret i16 %0
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23 }
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24
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25 define i32 @test_vminv_s32(<2 x i32> %a1) {
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26 ; CHECK: test_vminv_s32
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27 ; 2 x i32 is not supported by the ISA, thus, this is a special case
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
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30 ; CHECK-NEXT: ret
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31 entry:
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32 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
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33 ret i32 %vminv.i
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34 }
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35
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36 define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
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37 ; CHECK: test_vminvq_s8
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38 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
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39 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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40 ; CHECK-NEXT: ret
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41 entry:
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42 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
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43 %0 = trunc i32 %vminv.i to i8
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44 ret i8 %0
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45 }
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46
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
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48 ; CHECK: test_vminvq_s16
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49 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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50 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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51 ; CHECK-NEXT: ret
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52 entry:
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53 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
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54 %0 = trunc i32 %vminv.i to i16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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55 ret i16 %0
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56 }
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57
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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58 define i32 @test_vminvq_s32(<4 x i32> %a1) {
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59 ; CHECK: test_vminvq_s32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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60 ; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
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61 ; CHECK-NEXT: fmov w0, [[REGNUM]]
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62 ; CHECK-NEXT: ret
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63 entry:
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64 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
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65 ret i32 %vminv.i
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66 }
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67
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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68 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
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69 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
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70 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
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71 declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)
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72 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
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73 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
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74